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ds07-16801-2ea fujitsu microelectronics data sheet ?check sheet? is seen at the following support page url : http://edevice.fujitsu.com/micom/en-support/ ?check sheet? lists the minimal requirement items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest caut ions on development. copyright?2005-2008 fujitsu microelec tronics limited all rights reserved 2007.3 32-bit microcontroller cmos fr60lite mb91270 series mb91f273(s)/mb91f278(s)/mb91v280 description the mb91270 series is single chip microcontroller that builds various i/o resources and the bus control mecha- nisms into by using 32-bit efficient risc cpu for the built-in control being demanded for cpu processing high per- formance/high-speed. ram (for reading data) is included in order to support cpu to access to the vast address space and to speed up the execution of cpu instructions . this series is optimized to the embedded applications; automotive applications such as car audio or car air-co nditioning equipment that require high-performance cpu processing power. it is designed based on the fr-family* cpu. * : fr is the abbreviation of fujitsu risc controller. features ? fr cpu characteristics 32-bit risc, load/store architecture with a five-stage pipeline maximum operating frequency: 32 mhz (using the pll at an oscillation frequency of 4 mhz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle function entry/exit instructions, multip le - register load/store instructions : instructions adapted for high - level languages memory-to-memory transfer, bit manipulation, barrel shift instruction etc.: instruction optimized for embedded applications (continued)
mb91270 series 2 register interlock functions: easier assembler coding enabled built-in multiplier supporte d at the instruction level signed 32-bit multiplication: 5 cycles signed 16-bit multiplication: 3 cycles interrupt (pc, ps save): 6 cycles, 16 priority levels harvard architecture allowing program access and data access to be executed simultaneously instruction compatible with fr family ? external bus interface maximum operating frequency: 16 mhz can output full 24-bit address range (16 mbyte space) 8,16-bit data output unused data/address pin can be used as general-purpose i/o ports. capable of chip select output for completely independent four areas settable in 64 kbytes minimum. supports the following memory interfaces sram, rom/flash basic bus cycle: 2 cycles programmable automatic wait cycle generation function capable of inserting wait cycles for each area rdy input for external wait cycles ? built-in memory the peripheral circuits are described below. refer to ? product lineup? for the number of available channels on each model. ? dmac (dma controller) capable of simultaneous operation of up to five channels two forwarding factors (internal peripheral/software) ? bit search module (for realos) search for the first position of the bit ?1?/ ?0? changed in one word from the msb ? lin uarts (lin-uart) : up to 7 channels asynchronous (start-stop synchronous) communications, clock synchronous communications synch-break detection built-in baud rate generator on each channel supports spi (mode 2: clock synchronous communication mode) ? can controllers : 3 channels (max) high-speed transfer : 1 mbps 32 message buffer (128 message buffer on the mb91v280) (continued) mb91v280 mb91f273 (s) mb91f278 (s) rom/flash external sram flash 512 kbytes flash 512 kbytes f-bus ram 48 kbytes 24 kbytes 24 kbytes
mb91270 series 3 ? various timers 16-bit reload timer : 3 channels (including one channel for realos) the internal clock can be divided by 2, 8, or 32 16-bit free-running timer: 4 channels output compare module: 8 channels input capture module: 8 channels 8/16-bit ppg timer: 8-bit x 16 channels or 16-bit x 8 channels ? interrupt controller interrupt from internal peripheral software-selectable prio rity level (16 levels) ? d/a converter : 2 channels 8-bit or 10-bit resolution, r-2r type ? a/d converter: 24 channels (mb91v280 has an additional module with eight more channels) 10-bit resolution successive approximation conversion type conversion time : 3 s conversion mode (single conversion mode, continuous conversion mode) activation source (software, external trigger, peripheral interrupt) ? other interval timer/counter 8/16-bit up down counter : 8 bits 4 channels or 16 bits 2 channels 16-bit timebase timer / watchdog timer ? i 2 c bus interface* (400 kbps): 3 channels master/slave sending and receiving arbitration and clock synchronization ? hardware watchdog interval time: 569 ms (min), 771 ms (max) (use of self-oscillation circui t with timing (100 khz) ) ? i/o port pull-up/pull-down can be controlled independently for each pin. the input level for each pin can be set to either cm os schmitt trigger levels or cmos automotive schmitt trigger levels. the pin level can be read directly. max 82 ports ? other features internal oscillator circuit as clock source , allowing pll multiplication to be selected init is prepared as a reset pin. watchdog timer reset, software reset available low-power consumption modes are stop mode, sleep mode, and real time clock mode. supports low-power consumption operation with cpu operating at 32 khz (?s? without only product). gear function built-in timebase timer wild register (continued)
mb91270 series 4 (continued) output clock (clock monitor) clock modulator clock supervisor uses an internal self-oscillation circuit to monitor whether the main clock halts (mb91f278 (s) only) . package pga-401, lqfp-100 cmos technology (0.35 m) power supply voltage: 3.5 v to 5.5 v the 3.3 v supply to internal circuits is generated by an internal step-down circuit. * : i 2 c license purchase of fujitsu i 2 c components conveys a lic ense under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb91270 series 5 product lineup kind parameter mb91f273 (s) mb91f278 (s) mb91v280 package lqfp-100 lqfp-100 pga-401 built-in rom/ flash flash 512 kbytes flash 512 kbytes external sram ram 24 kbytes 24 kbytes 48 kbytes external bus address : 24 bits data : 16 bits (multiplex only) address : 24 bits data : 16 bits external interrupt 16 channels 40 channels dmac (dma controller) 5 channels clock modulator yes clock supervisor no yes clock monitor yes 32 khz sub-clock option (models without s-suffix part number only) yes real time clock yes can controllers 1 channel (32 message buffer) 3 channels (128 message buffer) lin uarts (lin-uart) 7 channels i 2 c interface 3 channels 16-bit reload timer 3 channels 8/16-bit up down counter 2 channels 16-bit free-run timer 4 channels input capture 8 channels output compare 8 channels 8/16-bit ppg 16-bit x 8 channels 8-bit x 16 channels 10-bit a/d converter 24 channels 24 channels + 8 channels 8/10-bit d/a converter no 2 channels pin pull-up/down refer to ? pin function? all pins input level selector refer to ? pin function? all pins debugging support wild register dsu4
mb91270 series 6 pin assignment (top view) (fpt-100p-m05) p25/a21/in1 p24/a20/in0 p23/a19/ppgf p22/a18/ppgd p21/a17/ppgb p20/a16/ppg9 p17/ad15/sck4 p16/ad14/sot4 p15/ad13/sin4 x0 x1 v ss v cc p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/sck6/int13 p04/ad04/sot6/int12 p03/ad03/sin6/int11 p02/ad02/sck5/int10 p01/ad01/sot5/int9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p26/a22/in2 p27/a23/in3 p30/as/in4 p31/rd/in5 p32/wr0/rx2/int10r p33/wr1/tx2 p34/brq/out4 p35/bgrnt/out5 p36/rdy/out6 p37/sysclk/out7 p40/(x0a) p41/(x1a) v cc v ss c p42/in6/rx1/int9r p43/in7/tx1 p44/sda0/frck0 p45/ain2/scl0/frck1 p46/bin2/sda1 p47/zin2/scl1 p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/bin1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p00/ad00/sin5/int8 pa1/tx0 pa0/rx0/int8r p97/out3 p96/out2/zin0 p95/out1/bin0 p94/out0/ain0 p93/ppg7/zin3/cs3 p92/ppg5/bin3/cs2 p91/ppg3/ain3/cs1 p90/ppg1/cs0 v ss v cc p87/sck1 p86/sot1 p85/sin1 p84/sck0/int15r p83/tot2/sot0 p82/tin2/sin0/int14r p81/tot0/int13r/ckot p80/tin0/int12r/adtg p77/an23/int7/scl2 p76/an22/int6/sda2 init md0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p54/an12/ain1 p55/an13/zin1 p56/an14/dao0 p57/an15/dao1 av cc avrh avrl av ss p60/an0/ppg0 p61/an1/ppg2 p62/an2/ppg4 p63/an3/ppg6 p64/an4/ppg8 p65/an5/ppga p66/an6/ppgc p67/an7/ppge v ss p70/an16/int0 p71/an17/int1 p72/an18/int2 p73/an19/int3 p74/an20/int4 p75/an21/int5 md2 md1 lqfp-100
mb91270 series 7 pin function * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 90 x1 x1 ob oscillator output pin 91 x0 x0 oa oscillator input pin 52 init init n reset input pin (?l? active) 49 to 51 md2 to md0 md2 to md0 j operation mode select input pins. connect to v cc or v ss directly. port 0 75 p00/ad00/ sin5/int8 p00 t general-purpose i/o port. this function is enabled in single-chip mode. ad00 external address/data bus i/o pin bit 0 this function is enabled when the external bus is enabled. int8 external interrupt request 8 input pin sin5 serial data input pin for lin-uart5 76 p01/ad01/ sot5/int9 p01 t general-purpose i/o port. this function is enabled in single-chip mode. ad01 external address/data bus i/o pin bit 1 this function is enabled when the external bus is enabled. int9 external interrupt request 9 input pin sot5 serial data output pin for lin-uart5 77 p02/ad02/ sck5/int10 p02 t general-purpose i/o port. this function is enabled in single-chip mode. ad02 external address/data bus i/o pin bit 2 this function is enabled when the external bus is enabled. int10 external interrupt request 10 input pin sck5 clock i/o pin for lin-uart5 78 p03/ad03/ sin6/int11 p03 t general-purpose i/o port. this function is enabled in single-chip mode. ad03 external address/data bus i/o pin bit 3 this function is enabled when the external bus is enabled. int11 external interrupt request 11 input pin sin6 serial data input pin for lin-uart6 79 p04/ad04/ sot6/int12 p04 t general-purpose i/o port. this function is enabled in single-chip mode. ad04 external address/data bus i/o pin bit 4 this function is enabled when the external bus is enabled. int12 external interrupt request 12 input pin sot6 serial data output pin for lin-uart6
mb91270 series 8 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 80 p05/ad05/ sck6/int13 p05 t general-purpose i/o port. this function is enabled in single-chip mode. ad05 external address/data bus i/o pin bit 5 this function is enabled when the external bus is enabled. int13 external interrupt request 13 input pin sck6 clock i/o pin for lin-uart6 81 p06/ad06/ int14 p06 t general-purpose i/o port. this function is enabled in single-chip mode. ad06 external address/data bus i/o pin bit 6 this function is enabled when the external bus is enabled. int14 external interrupt request 14 input pin 82 p07/ad07/ int15 p07 t general-purpose i/o port. this function is enabled in single-chip mode. ad07 external address/data bus i/o pin bit 7 this function is enabled when the external bus is enabled. int15 external interrupt request 15 input pin port 1 83 p10/ad08/ tin1 p10 t general-purpose i/o port. this function is enabled in single-chip mode. ad08 external address/data bus i/o pin bit 8 this function is enabled when the external bus is enabled. tin1 event input pin for reload timer 1 84 p11/ad09/ tot1 p11 t general-purpose i/o port. this function is enabled in single-chip mode. ad09 external address/data bus i/o pin bit 9 this function is enabled when the external bus is enabled. tot1 output pin for reload timer 1 85 p12/ad10/ sin3/ int11r p12 t general-purpose i/o port. this function is enabled in single-chip mode. ad10 external address/data bus i/o pin bit 10 this function is enabled when the external bus is enabled. sin3 serial data input pin for lin-uart3 int11r external interrupt request 11 input pin (set by eissr) 86 p13/ad11/ sot3 p13 t general-purpose i/o port. this function is enabled in single-chip mode. ad11 external address/data bus i/o pin bit 11 this function is enabled when the external bus is enabled. sot3 serial data output pin for lin-uart3
mb91270 series 9 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 87 p14/ad12/ sck3 p14 t general-purpose i/o port. this function is enabled in single-chip mode. ad12 external address/data bus i/o pin bit 12 this function is enabled when the external bus is enabled. sck3 clock i/o pin for lin-uart3 92 p15/ad13/ sin4 p15 t general-purpose i/o port. this function is enabled in single-chip mode. ad13 external address/data bus i/o pin bit 13 this function is enabled when the external bus is enabled. sin4 serial data input pin for lin-uart4 93 p16/ad14/ sot4 p16 t general-purpose i/o port. this function is enabled in single-chip mode. ad14 external address/data bus i/o pin bit 14 this function is enabled when the external bus is enabled. sot4 serial data output pin for lin-uart4 94 p17/ad15/ sck4 p17 t general-purpose i/o port. this function is enabled in single-chip mode. ad15 external address/data bus i/o pin bit 15 this function is enabled when the external bus is enabled. sck4 clock i/o pin for lin-uart4 port 2 95 p20/a16/ ppg9 p20 a general-purpose i/o port. this function is enabled in single-chip mode. a16 external address bus output pin bit 16 this function is enabled when the external bus is enabled. ppg9 output pin for ppg9 96 p21/a17/ ppgb p21 a general-purpose i/o port. this function is enabled in single-chip mode. a17 external address bus output pin bit 17 this function is enabled when the external bus is enabled. ppgb output pin for ppgb 97 p22/a18/ ppgd p22 a general-purpose i/o port. this function is enabled in single-chip mode. a18 external address bus output pin bit 18 this function is enabled when the external bus is enabled. ppgd output pin for ppgd
mb91270 series 10 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 98 p23/a19/ ppgf p23 a general-purpose i/o port. this function is enabled in single-chip mode. a19 external address bus output pin bit 19 this function is enabled when the external bus is enabled. ppgf output pin for ppgf 99, 100, 1, 2 p24/a20/in0 to p27/a23/in3 p24 to p27 a general-purpose i/o port. this function is enabled in single-chip mode. a20 to a23 external address bus output pins bits 20 to 23 this function is enabled when the external bus is enabled. in0 to in3 data sample input pins for input capture icu0 to icu3 port 3 3p30/as /in4 p30 a general-purpose i/o port. this function is enabled in single-chip mode. as external address strobe output pin this function is enabled when the external bus is enabled. in4 data sample input pin for input capture icu4 4p31/rd /in5 p31 a general-purpose i/o port. this function is enabled in single-chip mode. rd external read strobe output pin this function is enabled when the external bus is enabled. in5 data sample input pin for input capture icu5 5 p32/wr0 / rx2/ int10r p32 a general-purpose i/o port. this function is enabled in single-chip mode. wr0 external data bus write strobe output pin. enabled when the external bus is enabled. wr0 is used as the data write strobe for 8-bit access and as the upper 8 bits of the data in 16-bit access. rx2 can2 rx input pin (mb91v280 only) int10r external interrupt request 10 input pin (set by eissr) 6 p33/wr1 / tx2 p33 a general-purpose i/o port. this function is enabled in single-chip mode. wr1 write strobe output pin for lower 8 bits in external data bus enabled when the external bus is enabled and external bus 16-bit mode is selected. tx2 can2 tx output pin (mb91v280 only)
mb91270 series 11 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 7 p34/brq/ out4 p34 t (a) general-purpose i/o port. this function is enabled in single-chip mode. brq external bus request input pin enabled when the external bus and the bus request func- tions are enabled. (mb91v280 only) out4 waveform output pin for output compare ocu4. 8 p35/ bgrnt / out5 p35 a general-purpose i/o port. this function is enabled in single-chip mode. bgrnt external bus acknowledge output pin enabled when the external bus and the bus request functions are enabled. (mb91v280 only) out5 waveform output pin for output compare ocu5. 9 p36/rdy/ out6 p36 t general-purpose i/o port. this function is enabled in single-chip mode. rdy external ready input pin enabled when the external bus and the bus request func- tions are enabled. out6 waveform output pin for output compare ocu6. 10 p37/ sysclk/ out7 p37 a general-purpose i/o port. this function is enabled in single-chip mode. sysclk external clock output pin this function is enabled when the external bus is enabled. out7 waveform output pin for output compare ocu7. port 4 11, 12 p40/ (x0a) , p41/ (x1a) p40, p41 a general-purpose i/o port (s-suffix models) x0a, x1a wa wb sub-clock oscillator input pin (without s-suffix models) 16 p42/in6/ rx1/int9r p42 a general-purpose i/o port in6 data sample input pin for input capture icu6 rx1 can1 rx input pin (mb91v280 only) int9r external interrupt request 9 input pin (set by eissr) 17 p43/in7/ tx1 p43 a general-purpose i/o port in7 data sample input pin for input capture icu7 tx1 can1 tx output pin (mb91v280 only) 18 p44/sda0/ frck0 p44 c general-purpose i/o port sda0 serial data i/o pin for i 2 c0 frck0 16-bit input/output timer 0 input pin
mb91270 series 12 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 19 p45/ain2/ scl0/ frck1 p45 c general-purpose i/o port scl0 serial clock i/o pin for i 2 c0 frck1 16-bit input/output timer 1 input pin ain2 8/16-bit up-count input pin for up down counter 2/3 20 p46/bin2/ sda1 p46 c general-purpose i/o port sda1 serial clock i/o pin for i 2 c1 bin2 8/16-bit down-count input pin for up down counter 2/3 21 p47/zin2/ scl1 p47 c general-purpose i/o port scl1 serial clock i/o pin for i 2 c1 zin2 8/16-bit reset input pin for up down counter 2/3 port 5 22 p50/an8/ sin2 p50 d general-purpose i/o port an8 analog input pin of a/d converter sin2 serial data input pin for lin-uart2 23 p51/an9/ sot2 p51 d general-purpose i/o port an9 analog input pin of a/d converter sot2 serial data output pin for lin-uart2 24 p52/an10/ sck2 p52 d general-purpose i/o port an10 analog input pin of a/d converter sck2 clock i/o pin for lin-uart2 25 p53/an11/ bin1 p53 d general-purpose i/o port an11 analog input pin of a/d converter bin1 8-bit down-count input pin for 16-bit up down counter 1 26 p54/an12/ ain1 p54 d general-purpose i/o port an12 analog input pin of a/d converter ain1 8-bit up-count input pin for 16-bit up down counter 1 27 p55/an13/ zin1 p55 d general-purpose i/o port an13 analog input pin of a/d converter zin1 8-bit reset input pin for 16-bit up down counter 1 28 p56/an14/ dao0 p56 e general-purpose i/o port an14 analog input pin of a/d converter dao0 analog output pin 0 for d/a converter (mb91v280 only) 29 p57/an15/ dao1 p57 e general-purpose i/o port an15 analog input pin of a/d converter dao1 analog output pin 1 for d/a converter (mb91v280 only)
mb91270 series 13 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function port 6 34 to 41 p60/an0/ ppg0 to p67/an7/ ppge p60 to p67 d general-purpose i/o port an0 to an7 analog input pins of a/d converter ppg0 ppg2 ppg4 ppg6 ppg8 ppga ppgc ppge output pins for ppg port 7 43 to 48 p70/an16/ int0 to p75/an21/ int5 p70 to p75 d general-purpose i/o port an16 to an21 analog input pins of a/d converter int0 to int5 external interrupt request 0 to 5 input pin 53 p76/an22/ int6/sda2 p76 ca general-purpose i/o port an22 analog input pin of a/d converter int6 external interrupt request 6 input pin sda2 serial clock i/o pin for i 2 c2 54 p77/an23/ int7/scl2 p77 ca general-purpose i/o port an23 analog input pin of a/d converter int7 external interrupt request 7 input pin scl2 serial clock i/o pin for i 2 c2 port 8 55 p80/tin0/ int12r/ adtg p80 a general-purpose i/o port tin0 event input pin for reload timer 0 adtg trigger input pin for a/d converter int12r external interrupt request 12 input pin (set by eissr) 56 p81/tot0/ int13r/ ckot p81 a general-purpose i/o port tot0 output pin for reload timer 0 ckot output pin for clock monitor int13r external interrupt request 13 input pin (set by eissr) 57 p82/tin2/ sin0/int14r p82 a general-purpose i/o port sin0 serial data input pin for lin-uart0 tin2 event input pin for reload timer 2 int14r external interrupt request 14 input pin (set by eissr)
mb91270 series 14 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 58 p83/tot2/ sot0 p83 a general-purpose i/o port sot0 serial data output pin for lin-uart0 tot2 output pin for reload timer 2 59 p84/sck0/ int15r p84 a general-purpose i/o port sck0 clock i/o pin for lin-uart0 int15r external interrupt request 15 input pin (set by eissr) 60 p85/sin1 p85 a general-purpose i/o port sin1 serial data input pin for lin-uart1 61 p86/sot1 p86 a general-purpose i/o port sot1 serial data output pin for lin-uart1 62 p87/sck1 p87 a general-purpose i/o port sck1 clock i/o pin for lin-uart1 port 9 65 p90/ppg1/ cs0 p90 a general-purpose i/o port cs0 external chip select 0 this function is enabled when the external bus is enabled. ppg1 output pin for ppg1 66 p91/ppg3/ ain3/cs1 p91 a general-purpose i/o port cs1 external chip select 1 this function is enabled when the external bus is enabled. ppg3 output pin for ppg3 ain3 8-bit up-count input pin for up down counter 3 67 p92/ppg5/ bin3/cs2 p92 a general-purpose i/o port cs2 external chip select 2 this function is enabled when the external bus is enabled. ppg5 output pin for ppg5 bin3 8-bit down-count input pin for up down counter 3 68 p93/ppg7/ zin3/cs3 p93 a general-purpose i/o port cs3 external chip select 3 this function is enabled when the external bus is enabled. ppg7 output pin for ppg7 zin3 8-bit reset input pin for up down counter 3 69 p94/out0/ ain0 p94 a general-purpose i/o port out0 waveform output pin for output compare ocu0 ain0 16/8-bit up-count input pin for up down counter 0/1
mb91270 series 15 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function 70 p95/out1/ bin0 p95 a general-purpose i/o port out1 waveform output pin for output compare ocu1 bin0 8/16-bit down-count input pin for up down counter 0/1 71 p96/out2/ zin0 p96 a general-purpose i/o port out2 waveform output pin for output compare ocu2 zin0 8/16-bit reset input pin for up down counter 0/1 72 p97/out3 p97 a general-purpose i/o port out3 waveform output pin for output compare ocu3 port a 73 pa0/rx0/ int8r pa0 a general-purpose i/o port rx0 rx input pin for can0 int8r external interrupt request 8 input pin (set by eissr) 74 pa1/tx0 pa1 a general-purpose i/o port tx0 tx output pin for can0 port b (mb91v280 only) ? pb0 pb0 a general-purpose i/o port int8-2 external interrupt request 8 input pin (set by epfrb) sin5-2 serial data input pin for lin-uart5 (set by pfrb) ? pb1 pb1 a general-purpose i/o port int9-2 external interrupt request 9 input pin (set by epfrb) sot5-2 serial data output pin for lin-uart5 ? pb2 pb2 a general-purpose i/o port int10-2 external interrupt request 10 input pin (set by epfrb) sck5-2 clock i/o pin for lin-uart5 (set by pfrb) ? pb3 pb3 a general-purpose i/o port int11-2 external interrupt request 11 input pin (set by epfeb) sin6-2 serial data input pin for lin-uart6 (set by pfrb) ? pb4 pb4 a general-purpose i/o port int12-2 external interrupt request 12 input pin (set by epfrb) sot6-2 serial data output pin for lin-uart6 ? pb5 pb5 a general-purpose i/o port int13-2 external interrupt request 13 input pin (set by epfrb) sck6-2 clock i/o pin for lin-uart6 (set by pfrb) port c (mb91v280 only)
mb91270 series 16 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function ? pc0 pc0 a general-purpose i/o port out4-2 output pin for output compare 4 int0r external interrupt request 0 input pin (set by eissr) ? pc1 pc1 a general-purpose i/o port out5-2 output pin for output compare 5 int1r external interrupt request 1 input pin (set by eissr) ? pc2 pc2 a general-purpose i/o port sin3-2 serial data input pin for lin-uart3 (set by pfrc) int2r external interrupt request 2 input pin (set by eissr) ? pc3 pc3 a general-purpose i/o port sot3-2 serial data output pin for lin-uart3 int3r external interrupt request 3 input pin (set by eissr) ? pc4 pc4 a general-purpose i/o port sck3-2 clock i/o pin for lin-uart3 (set by pfrc) int4r external interrupt request 4 input pin (set by eissr) ? pc5 pc5 a general-purpose i/o port sin4-2 serial data input pin for lin-uart4 (set by pfrc) int5r external interrupt request 5 input pin (set by eissr) ? pc6 pc6 a general-purpose i/o port sot4-2 serial data output pin for lin-uart4 int6r external interrupt request 6 input pin (set by eissr) ? pc7 pc7 a general-purpose i/o port sck4-2 clock i/o pin for lin-uart4 (set by pfrc) int7r external interrupt request 7 input pin (set by eissr) port d (mb91v280 only) ? pd0 pd0 a general-purpose i/o port int16 external interrupt request 16 input pin ppg9-2 output pin for ppg9 (8) ? pd1 pd1 a general-purpose i/o port int17 external interrupt request 17 input pin ppgb-2 output pin for ppgb (a) ? pd2 pd2 a general-purpose i/o port int18 external interrupt request 18 input pin ppgd-2 output pin for ppgd (c)
mb91270 series 17 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function ? pd3 pd3 a general-purpose i/o port int19 external interrupt request 19 input pin ppgf-2 output pin for ppgf (e) ? pd4 pd4 a general-purpose i/o port int20 external interrupt request 20 input pin in0-2 input pin for input capture icu0 (set by pfrd) ? pd5 pd5 a general-purpose i/o port int21 external interrupt request 21 input pin in1-2 input pin for input capture icu1 (set by pfrd) ? pd6 pd6 a general-purpose i/o port int22 external interrupt request 22 input pin in2-2 input pin for input capture icu2 (set by pfrd) ? pd7 pd7 a general-purpose i/o port int23 external interrupt request 23 input pin in3-2 input pin for input capture icu3 (set by pfrd) port e (mb91v280 only) ? pe0 pe0 a general-purpose i/o port a00 external address bus output pin bit 0 this function is enabled when the external bus is enabled. int24 external interrupt request 24 input pin ? pe1 pe1 a general-purpose i/o port a01 external address bus output pin bit 1 this function is enabled when the external bus is enabled. int25 external interrupt request 25 input pin ? pe2 pe2 a general-purpose i/o port a02 external address bus output pin bit 2 this function is enabled when the external bus is enabled. int26 external interrupt request 26 input pin ? pe3 pe3 a general-purpose i/o port a03 external address bus output pin bit 3 this function is enabled when the external bus is enabled. int27 external interrupt request 27 input pin ? pe4 pe4 a general-purpose i/o port a04 external address bus output pin bit 4 this function is enabled when the external bus is enabled. int28 external interrupt request 28 input pin
mb91270 series 18 * : refer to ? i/o circuit type? for the i/o circuit type. (continued) pin no. pin name function name i/o circuit type* function ? pe5 pe5 a general-purpose i/o port a05 external address bus output pin bit 5 this function is enabled when the external bus is enabled. int29 external interrupt request 29 input pin ? pe6 pe6 a general-purpose i/o port a06 external address bus output pin bit 6 this function is enabled when the external bus is enabled. int30 external interrupt request 30 input pin ? pe7 pe7 a general-purpose i/o port a07 external address bus output pin bit 7 this function is enabled when the external bus is enabled. int31 external interrupt request 31 input pin port f (mb91v280 only) ? pf0 pf0 a general-purpose i/o port a08 external address bus output pin bit 8 this function is enabled when the external bus is enabled. int32 external interrupt request 32 input pin ? pf1 pf1 a general-purpose i/o port a09 external address bus output pin bit 9 this function is enabled when the external bus is enabled. int33 external interrupt request 33 input pin ? pf2 pf2 a general-purpose i/o port a10 external address bus output pin bit 10 this function is enabled when the external bus is enabled. int34 external interrupt request 34 input pin ? pf3 pf3 a general-purpose i/o port a11 external address bus output pin bit 11 this function is enabled when the external bus is enabled. int35 external interrupt request 35 input pin ? pf4 pf4 a general-purpose i/o port a12 external address bus output pin bit 12 this function is enabled when the external bus is enabled. int36 external interrupt request 36 input pin ? pf5 pf5 a general-purpose i/o port a13 external address bus output pin bit 13 this function is enabled when the external bus is enabled. int37 external interrupt request 37 input pin
mb91270 series 19 (continued) * : refer to ? i/o circuit type? for the i/o circuit type. pin no. pin name function name i/o circuit type* function ? pf6 pf6 a general-purpose i/o port a14 external address bus output pin bit 14 this function is enabled when the external bus is enabled. int38 external interrupt request 38 input pin ? pf7 pf7 a general-purpose i/o port a15 external address bus output pin bit 15 this function is enabled when the external bus is enabled. int39 external interrupt request 39 input pin port g (mb91v280 only) ? pg0 pg0 d general-purpose i/o port an24 analog input pin of a/d converter ? pg1 pg1 d general-purpose i/o port an25 analog input pin of a/d converter ? pg2 pg2 d general-purpose i/o port an26 analog input pin of a/d converter ? pg3 pg3 d general-purpose i/o port an27 analog input pin of a/d converter ? pg4 pg4 d general-purpose i/o port an28 analog input pin of a/d converter ? pg5 pg5 d general-purpose i/o port an29 analog input pin of a/d converter ? pg6 pg6 d general-purpose i/o port an30 analog input pin of a/d converter ? pg7 pg7 d general-purpose i/o port an31 analog input pin of a/d converter power supply pin 13, 63, 88 v cc ?? power supply (5 v) input pin 14, 42, 64, 89 v ss ?? power supply (0 v) input pin 15 c ?? power stabilization capacitance pin 30 av cc ?? analog power supply input pin 31 avrh ?? reference voltage input pin for the a/d converter ensure that a voltage greater than avrh is applied to av cc when turning this power supply on or off. 32 avrl ?? low reference voltage input pin for the a/d converter 33 av ss ?? analog v ss input pin
mb91270 series 20 i/o circuit type (continued) type circuit remarks a cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) resistor that can be set pull-up resistor : approx. 50 ? b cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) c cmos level output (i ol = 3 ma, i oh = ? 3 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) pout nout p-ch n-ch p-ch n-ch pull-up control pull-down control cmos hysteresis input automotive input standby control for disconnect input pout nout p-ch n-ch cmos hysteresis input automotive input standby control for disconnect input pout nout p-ch n-ch cmos hysteresis input automotive input standby control for disconnect input
mb91270 series 21 (continued) type circuit remarks ca cmos level output (i ol = 3 ma, i oh = ? 3 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) a/d analog input d cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) resistor that can be set pull-up resistor : approx. 50 ? a/d analog input pout nout p-ch n-ch cmos hysteresis input automotive input standby control for disconnect input analog input po u t no u t p-ch n-ch p-ch n-ch pull-up control pull-down control cmos hysteresis input automotive input standby control for disconnect input analog input
mb91270 series 22 (continued) type circuit remarks e cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) a/d analog input d/a analog output j cmos hysteresis input n cmos hysteresis input pull-up resistor value : approx. 50 k ? t cmos level output (i ol = 4 ma, i oh = ? 4 ma) cmos hysteresis input (with function to disconnect input during standby mode. ) automotive input (with function to disconnect input during standby mode. ) ttl (with function to disconnect input during standby mode. ) resistor that can be set pull-up resistor : approx. 50 k ? po u t no u t p-ch n-ch cmos hysteresis input automotive input standby control for disconnect input analog input analog output cmos hysteresis input cmos hysteresis input pull-up resistor pout nout p-ch n-ch p-ch n-ch pull-up control pull-down control cmos hysteresis input automotive input ttl input standby control for disconnect input
mb91270 series 23 (continued) type circuit remarks oa ob oscillation circuit high speed oscillation feedback resistance = approx. 1 m ? wa wb oscillation circuit low speed oscillation feedback resistance = approx. 10 m ? xout x1 x0 standby control signal xout x1a x0a standby control signal
mb91270 series 24 i/o cell list * : when the c and ca ports are set for the use of an i 2 c interface, the outputs are nch open drain outputs. otherwise, functions as a cmos output. pin input voltage type input analog line output driver remarks pull up/down (50 k ? ) cmos (c) cmos schmitt (cs) automotive (a) input stop a up/down switch cs/a switch stop ? 4 ma b ? cs/a switch stop ? 4 ma c* ? cs/a switch stop ? 3 ma i 2 c ca* ? cs/a switch stop input 3 ma i 2 c + a/dc d up/down switch cs/a switch stop input 4 ma a/dc e ? cs/a switch stop i/o 4 ma a/dc + d/ac j ? c ?? ? md[2 : 0] n up cs (initx) ?? ? init t up/down switch cs/a/ttl switch stop ? 4 ma has ttl input oa ob ?? stop ?? 4 mhz oscillator wa wb ?? stop ?? 32 khz oscillator form type v il v ih ccmos input v ss + 0.3 v v cc ? 0.3 v cs (initx) cmos schmitt trigger input (for init pin) 0.2 v cc 0.8 v cc cs cmos schmitt trigger input 0.3 v cc 0.7 v cc a cmos automotive schmitt trigger input 0.5 v cc 0.8 v cc t ttl input 0.8 v 2.1 v
mb91270 series 25 handling devices ? preventing latch-up latch-up may occur in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if an above-rating voltage is applied between v cc pin and v ss pin. a latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. when you use a cmos ic, do not exceed the maximum rating. ? treatment of unused pins do not leave an unused input pin open, since it may cause a malfunction. handle by, for example, using a pull- up or pull-down resistor. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations such as latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cera mic bypass capacitor of approximately 0.1 f between v cc and v ss near this device. ? crystal oscillator circuit noise near the x0, x1, x0a and x1a pins may cause the de vice to malfunction. design the printed circuit board so that x0, x1, x0a an d x1a pins the crystal oscillator (or ceramic oscillator), and the bypa ss capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0, x1, x0a and x1a pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillati onal characteristics of the crystal and this device. ? notes on using external clock when external clock is selected, supp ly it to x0 pin generally, and simultaneously the opposite phase clock to x0 must be supplied to x1 pin. however, in this case the stop mode (oscillation st op mode) must not be used. (this is because the x1 pin stops at high level output in stop mode.) note : the stop mode (oscillati on stop mode) cannot be used. x0 x1 using an external clock (normal)
mb91270 series 26 ? notes when using no sub-clock use a single-clock model if not using the sub-clock. always connect a resonator of 100 khz or less on dual clock models. ? treatment of nc or open pins pins marked as nc and open must be left open - circuit. ? mode pins (md0 to md2) these pins should be connected directly to v cc or v ss . to prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and v cc or v ss is as short as possible and the connection impedance is low. ? operation at start-up the init pin must be held at the ?l?level when turning on the power. ? source oscillation input at power on when turning the power on, maintain cl ock input until the device is releas ed from the oscilla tion stabilization wait state. ? caution on operations during pll clock mode on this microcontroller, if in case the crystal oscillator breaks off or an external re ference clock input stops while the pll clock mode is selected, a self -oscillator circuit contained in the pl l may continue its operation at its self-running frequency. however, fujitsu microelectronics will not guarantee re sults of operations if such failure occurs. ? external bus setting this device is guaranteed for use with a 16 mhz external bus. if the base clock is set to 32 mhz with divr1 (external bu s base clock division setting register) set to its initial value, the external bus also operates at 32 mhz. when changing the base clock, set the external bus so that it will not exceed 16 mhz. ? pull-up control the ac characteristics cannot be guaranteed if pull-up resistors are used for the pins used as external bus pins.
mb91270 series 27 block diagram 3 2 3 2 3 2 16 3 2 can controller f- bus - ram 8 /10- b it d/ac r- bus a d a pter fl as h/ ma s k rom 10- b it a/dc lin- uart0 i 2 c 400 khz f- bus d- bus 3 2 r- bus i- bus lin- uart sub -clock clock generator bit search module debug support dma controller external bus 24-bit address 16-bit data clock supervisor fr 60 lite cpu core harvard bus converter watchdog timer external bus i/f hardware watchdog 16-bit reload timer icu 16 bits clock monitor real time clock 16-bit free-run timer output compare 16 bits external interrupt up down counter 8/16 bits ppg 8/16 bits voltage regulator
mb91270 series 28 memory map note : the initial value for the emulation sram area on the mb91v280 is 512 kbytes (0000080000 h to 0000100000 h ) . an sram area is supported up to 1024 kbytes (0000050000 h to 0000150000 h ) 0000 0000 h 0000 0400 h 0001 0000 h 0002 0000 h 000 3 d 8 00 h 0004 0000 h 000 8 0000 h 0010 0000 h ffff ffff h 0002 0500 h 000 3 4000 h 000 3 a000 h i/o i/o can extern a l a re a extern a l a re a mb91v2 8 0 mb91f27 3 ( s )/ mb91f27 8 ( s ) i/o i/o can built-in ram 48 kbytes built-in ram 24 kbytes flash 512 kbytes emulation sram area direct addressing area refer to ? i/o map? access prohibited access prohibited access prohibited access prohibited access prohibited access prohibited
mb91270 series 29 i/o map how to read i/o map note : initial values of register bits are represented as follows : ? 1 ? : initial value ?1? ? 0 ? : initial value ?0? ? x ? : initial value ?undefined? ? - ? : no physical register present at this location access by any undescribed data access attribute is prohibited. address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b xxxxxxxx pdr1 [r/w] b xxxxxxxx pdr2 [r/w] b xxxxxxxx pdr3 [r/w] b xxxxxxxx t-unit port data register read/write attribute, access unit (b : byte, h : halfword, w : word) initial value after reset register name (first-column register at address 4n; second-column register at 4n + 1, etc.) location of left-most register (when using word access, the register in column 1 is in the msb side of the data.)
mb91270 series 30 (continued) address register block + 0 + 1 + 2 + 3 000000 h pdr0 [r/w] b, h xxxxxxxx pdr1 [r/w] b, h xxxxxxxx pdr2 [r/w] b, h xxxxxxxx pdr3 [r/w] b, h xxxxxxxx port data registers (pdrb to pdrg are only available on the mb91v280.) 000004 h pdr4 [r/w] b, h xxxxxxxx pdr5 [r/w] b, h xxxxxxxx pdr6 [r/w] b, h xxxxxxxx pdr7 [r/w] b, h xxxxxxxx 000008 h pdr8 [r/w] b, h xxxxxxxx pdr9 [r/w] b, h xxxxxxxx pdra [r/w] b, h ------xx pdrb [r/w] b, h --xxxxxx 00000c h pdrc [r/w] b, h xxxxxxxx pdrd [r/w] b, h xxxxxxxx pdre [r/w] b, h xxxxxxxx pdrf [r/w] b, h xxxxxxxx 000010 h pdrg [r/w] b, h xxxxxxxx ? 000014 h to 00003c h ? system reserved 000040 h eirr0 [r/w] 00000000 enir [r/w] 00000000 elvr0 [r/w] 00000000 00000000 ext. int 0-7 000044 h dicr [r/w] -------0 hrcl [r, r/w] 0--11111 ? dly / i-unit 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r, rw] 00000000 00000000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r, rw] 00000000 00000000 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ?? tmcsr2 [r, rw] 00000000 00000000 000060 h scr0 [r, r/w] 00000000 smr0 [w, r/w] 00000000 ssr0 [r, r/w] 00001000 rdr0/trd0 [r/w] 00000000 lin-uart 0 000064 h escr0 [r/w] 00000100 eccr0 [r, w, r/w] 000000xx bgr10 [r/w] 00000000 bgr00 [r/w] 00000000 000068 h scr5 [r, r/w] 00000000 smr5 [w, r/w] 00000000 ssr5 [r, r/w] 00001000 rdr5/trd5 [r/w] 00000000 lin-uart 5 00006c h escr5 [r/w] 00000100 eccr5 [r, w, r/w] 000000xx bgr15 [r/w] 00000000 bgr05 [r/w] 00000000
mb91270 series 31 (continued) address register block + 0 + 1 + 2 + 3 000070 h scr6 [r, r/w] 00000000 smr6 [w, r/w] 00000000 ssr6 [r, r/w] 00001000 rdr6/trd6 [r/w] 00000000 lin-uart 6 000074 h escr6 [r/w] 00000100 eccr6 [r, w, r/w] 000000xx bgr16 [r/w] 00000000 bgr06 [r/w] 00000000 000078 h to 0000ac h ? system reserved 0000b0 h scr1 [r, r/w] 00000000 smr1 [w, r/w] 00000000 ssr1 [r, r/w] 00001000 rdr1/trd1 [r/w] 00000000 lin-uart 1 0000b4 h escr1 [r/w] 00000100 eccr1 [r, w, r/w] 000000xx bgr11 [r/w] 00000000 bgr01 [r/w] 00000000 0000b8 h scr2 [r, r/w] 00000000 smr2 [w, r/w] 00000000 ssr2 [r, r/w] 00001000 rdr2/trd2 [r/w] 00000000 lin-uart 2 0000bc h escr2 [r/w] 00000100 eccr2 [r, w, r/w] 000000xx bgr12 [r/w] 00000000 bgr02 [r/w] 00000000 0000c0 h scr3 [r, r/w] 00000000 smr3 [w, r/w] 00000000 ssr3 [r, r/w] 00001000 rdr3/trd3 [r/w] 00000000 lin-uart 3 0000c4 h escr3 [r/w] 00000100 eccr3 [r, w, r/w] 000000xx bgr13 [r/w] 00000000 bgr03 [r/w] 00000000 0000c8 h scr4 [r, r/w] 00000000 smr4 [w, r/w] 00000000 ssr4 [r, r/w] 00001000 rdr4/trd4 [r/w] 00000000 lin-uart 4 0000cc h escr4 [r/w] 00000100 eccr4 [r, w, r/w] 000000xx bgr14 [r/w] 00000000 bgr04 [r/w] 00000000 0000d0 h eirr1 [r/w] 00000000 enir1 [r/w] 00000000 elvr1 [r/w] 00000000 00000000 ext. int 8 to 15 0000d4 h tctdt0 [r/w] h 00000000 00000000 ? tccs0 [r/w] b 00000000 free-run timer 0 0000d8 h tctdt1 [r/w] h 00000000 00000000 ? tccs1 [r/w] b 00000000 free-run timer 1 0000dc h tctdt2 [r/w] h 00000000 00000000 ? tccs2 [r/w] b 00000000 free-run timer 2 0000e0 h tctdt3 [r/w] h 00000000 00000000 ? tccs3 [r/w] b 00000000 free run timer 3
mb91270 series 32 (continued) address register block + 0 + 1 + 2 + 3 0000e4 h ipcp1 [r] xxxxxxxx xxxxxxxx ipcp0 [r] xxxxxxxx xxxxxxxx input capture unit 0, 1 0000e8 h ? ics01 [r/w] 00000000 0000ec h ipcp3 [r] xxxxxxxx xxxxxxxx ipcp2 [r] xxxxxxxx xxxxxxxx input capture unit 2, 3 0000f0 h ? ics23 [r/w] 00000000 0000f4 h ipcp5 [r] xxxxxxxx xxxxxxxx ipcp4 [r] xxxxxxxx xxxxxxxx input capture unit 4, 5 0000f8 h ? ics45 [r/w] 00000000 0000fc h ipcp7 [r] xxxxxxxx xxxxxxxx ipcp6 [r] xxxxxxxx xxxxxxxx input capture unit 6, 7 000100 h ? ics67 [r/w] 00000000 000104 h ? system reserved 000108 h occp1 [r/w] xxxxxxxx xxxxxxxx occp0 [r/w] xxxxxxxx xxxxxxxx output compare 1/0 00010c h occp3 [r/w] xxxxxxxx xxxxxxxx occp2 [r/w] xxxxxxxx xxxxxxxx output compare 3/2 000110 h ocs23 [r/w] 11101100 00001100 ocs01 [r/w] 11101100 00001100 output compare 3 to 0 ctrl. 000114 h occp5 [r/w] xxxxxxxx xxxxxxxx occp4 [r/w] xxxxxxxx xxxxxxxx output compare 5/4 000118 h occp7 [r/w] xxxxxxxx xxxxxxxx occp6 [r/w] xxxxxxxx xxxxxxxx output compare 7/6 00011c h ocs67 [r/w] 11101100 00001100 ocs45 [r/w] 11101100 00001100 output compare 7 to 4 ctrl. 000120 h to 00012c h ? system reserved 000130 h eirr2 [r/w] 00000000 enir2 [r/w] 00000000 elvr2 [r/w] 00000000 00000000 ext. int 16 to 23 000134 h eirr3 [r/w] 00000000 enir3 [r/w] 00000000 elvr3 [r/w] 00000000 00000000 ext. int 24 to 31 (mb91v280 only) 000138 h eirr4 [r/w] 00000000 enir4 [r/w] 00000000 elvr4 [r/w] 00000000 00000000 ext. int 32 to 39 (mb91v280 only) 00013c h ? dacr [r/w] -----000 dadr0 [r/w] ------00 00000000 d/a converter (mb91v280 only) 000140 h dadr1 [r/w] ------00 00000000 ? dadbl [r/w] -------0
mb91270 series 33 (continued) address register block + 0 + 1 + 2 + 3 000144 h ? wtdbl [r/w] b ------00 wtcr [r/w] b, h 00000000 000-00-x real time clock 000148 h ? wtbr [r/w] b ---xxxxx xxxxxxxx xxxxxxxx 00014c h wthr [r/w] b, h xxxxxxxx wtmr [r/w] b, h xxxxxxxx wtsr [r/w] b --xxxxxx ? 000150 h aderh [r/w] 00000000 00000000 aderl [r/w] 00000000 00000000 a/d converter 000154 h adcs1 [r/w] 00000000 adcs0 [r, r/w] 00000000 adcr1 [r] ------xx adcr0 [r] xxxxxxxx 000158 h adct1 [r/w] 00010000 adct0 [r/w] 00101100 adsch [r/w] ---00000 adech [r/w] ---00000 00015c h cucr [r/w] b, h, w -------- ---00000 cutd [r/w] b, h, w 10000000 00000000 clock calibration (mb91v280 and without s-suffix models only) 000160 h cutr1 [r] b, h, w -------- 00000000 cutr2 [r] b, h, w 00000000 00000000 000164 h to 00016c h ? system reserved 000170 h udrc1 [w] b, h 00000000 udrc0 [w] b, h 00000000 udcr1 [r] b, h 00000000 udcr0 [r] b, h 00000000 up down counter 0/1 000174 h udcch0 [r/w] b, h 00000000 udccl0 [r/w] b, h -0000000 ? udcs0 [r/w] b 00000000 000178 h udcch1 [r/w] b, h -0000000 udccl1 [r/w] b, h -0000000 ? udcs1 [r/w] b 00000000 00017c h ? system reserved 000180 h udrc3 [w] b, h 00000000 udrc2 [w] b, h 00000000 udcr3 [r] b, h 00000000 udcr2 [r] b, h 00000000 up down counter 2/3 000184 h udcch2 [r/w] b, h 00000000 udccl2 [r/w] b, h -0000000 ? udcs2 [r/w] b 00000000 000188 h udcch3 [r/w] b, h -0000000 udccl3 [r/w] b, h -0000000 ? udcs2 [r/w] b 00000000 00018c h ? system reserved 000190 h ad2erh [r/w] 00000000 00000000 ad2erl [r/w] 00000000 00000000 a/d converter 2 (mb91v280 only) 000194 h ad2cs1 [r/w] 00000000 ad2cs0 [r, r/w] 00000000 ad2cr1 [r] ------xx ad2cr0 [r] xxxxxxxx 000198 h ad2ct1 [r/w] 00010000 ad2ct0 [r/w] 00101100 ad2sch [r/w] ---00000 ad2ech [r/w] ---00000
mb91270 series 34 (continued) address register block + 0 + 1 + 2 + 3 00019c h ? system reserved 0001a0 h cmpr [r/w] b, h --000010 11111101 ? cmcr [r/w] b, h -0010000 clock modulator 0001a4 h cmt1 [r/w] b, h, w 00000000 10000000 cmt2 [r/w] b, h, w 00000000 00000000 0001a8 h canpre [r, r/w] 00000000 ? eissr [r/w] b, h 00000000 00000000 can clock presc / ext. int. source sel. 0001ac h ? system reserved 0001b0 h prlh0 [r/w] b, h, w xxxxxxxx prll0 [r/w] b, h, w xxxxxxxx prlh1 [r/w] b, h, w xxxxxxxx prll1 [r/w] b, h, w xxxxxxxx ppg0 to ppg3 0001b4 h prlh2 [r/w] b, h, w xxxxxxxx prll2 [r/w] b, h, w xxxxxxxx prlh3 [r/w] b, h, w xxxxxxxx prll3 [r/w] b, h, w xxxxxxxx 0001b8 h ppgc0 [r/w] b, h, w 0000000x ppgc1 [r/w] b, h, w 0000000x ppgc2 [r/w] b, h, w 0000000x ppgc3 [r/w] b, h, w 0000000x 0001bc h ? system reserved 0001c0 h prlh4 [r/w] b, h, w xxxxxxxx prll4 [r/w] b, h, w xxxxxxxx prlh5 [r/w] b, h, w xxxxxxxx prll5 [r/w] b, h, w xxxxxxxx ppg4 to ppg7 0001c4 h prlh6 [r/w] b, h, w xxxxxxxx prll6 [r/w] b, h, w xxxxxxxx prlh7 [r/w] b, h, w xxxxxxxx prll7 [r/w] b, h, w xxxxxxxx 0001c8 h ppgc4 [r/w] b, h, w 0000000x ppgc5 [r/w] b, h, w 0000000x ppgc6 [r/w] b, h, w 0000000x ppgc7 [r/w] b, h, w 0000000x 0001cc h ? system reserved 0001d0 h prlh8 [r/w] b, h, w xxxxxxxx prll8 [r/w] b, h, w xxxxxxxx prlh9 [r/w] b, h, w xxxxxxxx prll9 [r/w] b, h, w xxxxxxxx ppg8 to ppgb 0001d4 h prlha [r/w] b, h, w xxxxxxxx prlla [r/w] b, h, w xxxxxxxx prlhb [r/w] b, h, w xxxxxxxx prllb [r/w] b, h, w xxxxxxxx 0001d8 h ppgc8 [r/w] b, h, w 0000000x ppgc9 [r/w] b, h, w 0000000x ppgca [r/w] b, h, w 0000000x ppgcb [r/w] b, h, w 0000000x 0001dc h ? system reserved
mb91270 series 35 (continued) address register block + 0 + 1 + 2 + 3 0001e0 h prlhc [r/w] b, h, w xxxxxxxx prllc [r/w] b, h, w xxxxxxxx prlhd [r/w] b, h, w xxxxxxxx prlld [r/w] b, h, w xxxxxxxx ppgc to ppgf 0001e4 h prlhe [r/w] b, h, w xxxxxxxx prlle [r/w] b, h, w xxxxxxxx prlhf [r/w] b, h, w xxxxxxxx prllf [r/w] b, h, w xxxxxxxx 0001e8 h ppgcc [r/w] b, h, w 0000000x ppgcd [r/w] b, h, w 0000000x ppgce [r/w] b, h, w 0000000x ppgcf [r/w] b, h, w 0000000x 0001ec h ? system reserved 0001f0 h ppgtrg [r/w] b, h, w 00000000 00000000 ppgrevc [r/w] b, h, w 00000000 00000000 ppg0 to ppgf enable / reverse 0001f4 h ppgswap [r/w] b 00000000 ? ppg0 to ppgf output swap 0001f8 h cmclkr [r/w] b ----0000 ? clock monitor 0001fc h ? system reserved 000200 h dmaca0 [r/w] 00000000 00000000 00000000 00000000 dmac 000204 h dmacb0 [r/w] 00000000 00000000 00000000 00000000 000208 h dmaca1 [r/w] 00000000 00000000 00000000 00000000 00020c h dmacb1 [r/w] 00000000 00000000 00000000 00000000 dmac 000210 h dmaca2 [r/w] 00000000 00000000 00000000 00000000 000214 h dmacb2 [r/w] 00000000 00000000 00000000 00000000 000218 h dmaca3 [r/w] 00000000 00000000 00000000 00000000 00021c h dmacb3 [r/w] 00000000 00000000 00000000 00000000 000220 h dmaca4 [r/w] 00000000 00000000 00000000 00000000 000224 h dmacb4 [r/w] 00000000 00000000 00000000 00000000 000228 h to 00023c h ? system reserved
mb91270 series 36 (continued) address register block + 0 + 1 + 2 + 3 000240 h dmacr [r/w] 0xx00000 xxxxxxxx xxxxxxxx xxxxxxxx dmac 000244 h to 0003ec h ? system reserved 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddr0 [r/w] b, h 00000000 ddr1 [r/w] b, h 00000000 ddr2 [r/w] b, h 00000000 ddr3 [r/w] b, h 00000000 data direction registers (ddrb to ddrg are only available on the mb91v280) 000404 h ddr4 [r/w] b, h 00000000 ddr5 [r/w] b, h 00000000 ddr6 [r/w] b, h 00000000 ddr7 [r/w] b, h 00000000 000408 h ddr8 [r/w] b, h 00000000 ddr9 [r/w] b, h 00000000 ddra [r/w] b, h ------00 ddrb [r/w] b, h --000000 00040c h ddrc [r/w] b, h 00000000 ddrd [r/w] b, h 00000000 ddre [r/w] b, h 00000000 ddrf [r/w] b, h 00000000 000410 h ddrg [r/w] b, h 00000000 ? 000414 h to 00041c h ? system reserved 000420 h pfr0 [r/w] b, h 00000000 pfr1 [r/w] b, h 00000000 pfr2 [r/w] b, h 00000000 pfr3 [r/w] b, h 00000000 port function registers (pfrb to pfrg are only available on the mb91v280) 000424 h pfr4 [r/w] b, h 00000000 pfr5 [r/w] b, h 00000000 pfr6 [r/w] b, h 00000000 pfr7 [r/w] b, h 00000000 000428 h pfr8 [r/w] b, h 00000000 pfr9 [r/w] b, h 00000000 pfra [r/w] b, h ------00 pfrb [r/w] b, h --000000 00042c h pfrc [r/w] b, h 00000000 pfrd [r/w] b, h 00000000 pfre [r/w] b, h 00000000 pfrf [r/w] b, h 00000000 000430 h pfrg [r/w] b, h 00000000 ?
mb91270 series 37 (continued) address register block + 0 + 1 + 2 + 3 000434 h to 00043c h ? system reserved 000440 h icr00 [r, r/w] ---11111 icr01 [r, r/w] ---11111 icr02 [r, r/w] ---11111 icr03 [r, r/w] ---11111 interrupt control unit 000444 h icr04 [r, r/w] ---11111 icr05 [r, r/w] ---11111 icr06 [r, r/w] ---11111 icr07 [r, r/w] ---11111 000448 h icr08 [r, r/w] ---11111 icr09 [r, r/w] ---11111 icr10 [r, r/w] ---11111 icr11 [r, r/w] ---11111 00044c h icr12 [r, r/w] ---11111 icr13 [r, r/w] ---11111 icr14 [r, r/w] ---11111 icr15 [r, r/w] ---11111 000450 h icr16 [r, r/w] ---11111 icr17 [r, r/w] ---11111 icr18 [r, r/w] ---11111 icr19 [r, r/w] ---11111 000454 h icr20 [r, r/w] ---11111 icr21 [r, r/w] ---11111 icr22 [r, r/w] ---11111 icr23 [r, r/w] ---11111 000458 h icr24 [r, r/w] ---11111 icr25 [r, r/w] ---11111 icr26 [r, r/w] ---11111 icr27 [r, r/w] ---11111 00045c h icr28 [r, r/w] ---11111 icr29 [r, r/w] ---11111 icr30 [r, r/w] ---11111 icr31 [r, r/w] ---11111 000460 h icr32 [r, r/w] ---11111 icr33 [r, r/w] ---11111 icr34 [r, r/w] ---11111 icr35 [r, r/w] ---11111 000464 h icr36 [r, r/w] ---11111 icr37 [r, r/w] ---11111 icr38 [r, r/w] ---11111 icr39 [r, r/w] ---11111 000468 h icr40 [r, r/w] ---11111 icr41 [r, r/w] ---11111 icr42 [r, r/w] ---11111 icr43 [r, r/w] ---11111 00046c h icr44 [r, r/w] ---11111 icr45 [r, r/w] ---11111 icr46 [r, r/w] ---11111 icr47 [r, r/w] ---11111 000470 h to 00047c h ? system reserved 000480 h rsrr [r, r/w] 10000000 stcr [r/w] 00110011 tbcr [r/w] 00xxxx00 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h ? osccr [r/w] xxxxxxx0 ? 00048c h ? system reserved 000490 h oscr [w, r/w] 00000000 ? stb. wait timer
mb91270 series 38 (continued) address register block + 0 + 1 + 2 + 3 000494 h to 0004a8 h ? system reserved 0004ac h ? csvcr [r/w] 0001xx00 ? clock supervisor 0004b0 h to 0004fc h ? system reserved 000500 h pper0 [r/w] b, h 00000000 pper1 [r/w] b, h 00000000 pper2 [r/w] b, h 00000000 pper3 [r/w] b, h 00000000 port pull-up/down enable registers (pperb to pperg are only available on the mb91v280) 000504 h pper4 [r/w] b, h 00000000 pper5 [r/w] b, h 00000000 pper6 [r/w] b, h 00000000 pper7 [r/w] b, h 00000000 000508 h pper8 [r/w] b, h 00000000 pper9 [r/w] b, h 00000000 ppera [r/w] b, h ------00 pperb [r/w] b, h --000000 00050c h pperc [r/w] b, h 00000000 pperd [r/w] b, h 00000000 ppere [r/w] b, h 00000000 pperf [r/w] b, h 00000000 000510 h pperg [r/w] b, h 00000000 ? 000514 h to 00051c h ? system reserved 000520 h ppcr0 [r/w] b, h 00000000 ppcr1 [r/w] b, h 00000000 ppcr2 [r/w] b, h 00000000 ppcr3 [r/w] b, h 00000000 port pull-up/down control registers (ppcrb to ppcrg are only available on the mb91v280) 000524 h ppcr4 [r/w] b, h 00000000 ppcr5 [r/w] b, h 00000000 ppcr6 [r/w] b, h 00000000 ppcr7 [r/w] b, h 00000000 000528 h ppcr8 [r/w] b, h 00000000 ppcr9 [r/w] b, h 00000000 ppcra [r/w] b, h ------00 ppcrb [r/w] b, h --000000 00052c h ppcrc [r/w] b, h 00000000 ppcrd [r/w] b, h 00000000 ppcre [r/w] b, h 00000000 ppcrf [r/w] b, h 00000000 000530 h ppcrg [r/w] b, h 00000000 ? 000534 h to 00053c h ? system reserved
mb91270 series 39 (continued) address register block + 0 + 1 + 2 + 3 000540 h pilr0 [r/w] b, h 00000000 pilr1 [r/w] b, h 00000000 pilr2 [r/w] b, h 00000000 pilr3 [r/w] b, h 00000000 port input level select registers (pilrb to pilrg are only available on the mb91v280) 000544 h pilr4 [r/w] b, h 00000000 pilr5 [r/w] b, h 00000000 pilr6 [r/w] b, h 00000000 pilr7 [r/w] b, h 00000000 000548 h pilr8 [r/w] b, h 00000000 pilr9 [r/w] b, h 00000000 pilra [r/w] b, h ------00 pilrb [r/w] b, h --000000 00054c h pilrc [r/w] b, h 00000000 pilrd [r/w] b, h 00000000 pilre [r/w] b, h 00000000 pilrf [r/w] b, h 00000000 000550 h pilrg [r/w] 00000000 ? 000554 h to 00055c h ? system reserved 000560 h ibcr0 [r/w] 00000000 ibsr0 [r] 00000000 itbah0 [r/w] ------00 itbal0 [r/w] 00000000 i 2 c 0 000564 h itmkh0 [r/w, r] 00----11 itmkl0 [r/w] 11111111 ismk0 [r/w] 01111111 isba0 [r/w] -0000000 000568 h ? idar0 [r/w] 00000000 iccr0 [r/w] -0011111 ? 00056c h ? system reserved 000570 h ibcr1 [r/w] 00000000 ibsr1 [r] 00000000 itbah1 [r/w] ------00 itbal1 [r/w] 00000000 i 2 c 1 000574 h itmkh1 [r/w, r] 00----11 itmkl1 [r/w] 11111111 ismk1 [r/w] 01111111 isba1 [r/w] -0000000 000578 h ? idar1 [r/w] 00000000 iccr1 [r/w] -0011111 ? 00057c h ? system reserved 000580 h ibcr2 [r/w] 00000000 ibsr2 [r] 00000000 itbah2 [r/w] ------00 itbal2 [r/w] 00000000 i 2 c 2 000584 h itmkh2 [r/w, r] 00----11 itmkl2 [r/w] 11111111 ismk2 [r/w] 01111111 isba2 [r/w] -0000000 000588 h ? idar2 [r/w] 00000000 iccr2 [r/w] -0011111 ? 00058c h ? system reserved 000590 h to 0005f8 h ? system reserved 0005fc h ? hwdcs [r/w] b, h 00011000 ? hardware watchdog
mb91270 series 40 (continued) address register block + 0 + 1 + 2 + 3 000600 h epfr0 [r/w] b, h 00000000 epfr1 [r/w] b, h 00000000 epfr2 [r/w] b, h 00000000 epfr3 [r/w] b, h 00000000 extra port function register (epfrb to epfrg are only available on the mb91v280) 000604 h epfr4 [r/w] b, h 00000000 epfr5 [r/w] b, h 00000000 epfr6 [r/w] b, h 00000000 epfr7 [r/w] b, h 00000000 000608 h epfr8 [r/w] b, h 00000000 epfr9 [r/w] b, h 00000000 epfra [r/w] b, h ------00 epfrb [r/w] b, h --000000 00060c h epfrc [r/w] b, h 00000000 epfrd [r/w] b, h 00000000 epfre [r/w] b, h 00000000 epfrf [r/w] b, h 00000000 000610 h epfrg [r/w] b, h 00000000 ? 000614 h to 00061c h ? system reserved 000620 h pidr0 [r] b, h xxxxxxxx pidr1 [r] b, h xxxxxxxx pidr2 [r] b, h xxxxxxxx pidr3 [r] b, h xxxxxxxx input data direct read data register (pidrb to pdirg are only available on the mb91v280) 000624 h pidr4 [r] b, h xxxxxxxx pidr5 [r] b, h xxxxxxxx pidr6 [r] b, h xxxxxxxx pidr7 [r] b, h xxxxxxxx 000628 h pidr8 [r] b, h xxxxxxxx pidr9 [r] b, h xxxxxxxx pidra [r] b, h ------xx pidrb [r] b, h --xxxxxx 00062c h pidrc [r] b, h xxxxxxxx pidrd [r] b, h xxxxxxxx pidre [r] b, h xxxxxxxx pidrf [r] b, h xxxxxxxx 000630 h pidrg [r] b, h xxxxxxxx ? 000634 h to 00063c h ? system reserved 000640 h asr0 [r/w] 00000000 00000000 acr0 [r/w] 00110*00 00000000 t-unit 000644 h asr1 [r/w] xxxxxxxx xxxxxxxx acr1 [r/w] xxxx0x00 00x0xxxx 000648 h asr2 [r/w] xxxxxxxx xxxxxxxx acr2 [r/w] xxxx0x00 00x0xxxx 00064c h asr3 [r/w] xxxxxxxx xxxxxxxx acr3 [r/w] 01xx0x00 00x0xxxx
mb91270 series 41 (continued) address register block + 0 + 1 + 2 + 3 000650 h to 00065c h ? t-unit 000660 h awr0 [r/w] 01110000 01011011 awr1 [r/w] xxxx0000 xx0x1xxx 000664 h awr2 [r/w] 0xxx0000 xx0x1xxx awr3 [r/w] 0xxx0000 0x0x1xxx 000668 h to 00067c h ? 000680 h cser [r/w] ----0001 ? 000684 h to 0007f8 h ? system reserved 0007fc h ? modr [w] xxxxxxxx ? mode register 000800 h to 000ffc h ? system reserved 001000 h ? dmasa0 [r/w] ----0000 00000000 00000000 dmac 001004 h ? dmada0 [r/w] ----0000 00000000 00000000 001008 h ? dmasa1 [r/w] ----0000 00000000 00000000 00100c h ? dmada1 [r/w] ----0000 00000000 00000000 001010 h ? dmasa2 [r/w] ----0000 00000000 00000000 001014 h ? dmada2 [r/w] ----0000 00000000 00000000 001018 h ? dmasa3 [r/w] ----0000 00000000 00000000 00101c h ? dmada30 [r/w] ----0000 00000000 00000000 001020 h ? dmasa4 [r/w] 00000000 00000000 00000000 001024 h ? dmada4 [r/w] 00000000 00000000 00000000 00102b h to 006ffc h ? system reserved
mb91270 series 42 (continued) address register block + 0 + 1 + 2 + 3 007000 h flcr [r/w] 0110x000 ? flash i/f 007004 h flwc [r/w] 00000011 ? 007008 h to 01fffc h ? system reserved 020000 h ctrlr0 [r, r/w] 00000000 00000001 statr0 [r, r/w] 00000000 00000000 can 0 020004 h errcnt0 [r] 00000000 00000000 btr0 [r, r/w] 00100011 00000001 020008 h intr0 [r] 00000000 00000000 testr0 [r, r/w] 00000000 00000000 can 0 02000c h brper0 [r, r/w] 00000000 00000000 ? 020010 h if1creq0 [r, r/w] 00000000 00000001 if1cmsk0 [r, r/w] 00000000 00000000 020014 h if1msk20 [r, r/w] 11111111 11111111 if1msk10 [r, r/w] 11111111 11111111 020018 h if1arb20 [r/w] 00000000 00000000 if1arb10 [r/w] 00000000 00000000 02001c h if1mctr0 [r, r/w] 00000000 00000000 ? 020020 h if1dta10 [r/w] xxxxxxxx xxxxxxxx if1dta20 [r/w] xxxxxxxx xxxxxxxx 020024 h if1dtb10 [r/w] xxxxxxxx xxxxxxxx if1dtb20 [r/w] xxxxxxxx xxxxxxxx 020030 h to 02003c h system reserved (if1 data mirror, little endian byte ordering) 020040 h if2creq0 [r, r/w] 00000000 00000001 if2cmsk0 [r, r/w] 00000000 00000000 020044 h if2msk20 [r, r/w] 11111111 11111111 if2msk10 [r, r/w] 11111111 11111111 020048 h if2arb20 [r/w] 00000000 00000000 if2arb10 [r/w] 00000000 00000000 02004c h if2mctr0 [r, r/w] 00000000 00000000 ? 020050 h if2dta10 [r/w] xxxxxxxx xxxxxxxx if2dta20 [r/w] xxxxxxxx xxxxxxxx 020054 h if2dtb10 [r/w] xxxxxxxx xxxxxxxx if2dtb20 [r/w] xxxxxxxx xxxxxxxx
mb91270 series 43 (continued) address register block + 0 + 1 + 2 + 3 020060 h to 02007c h system reserved (if2 data mirror, little endian byte ordering) can 0 020080 h treqr20 [r] 00000000 00000000 treqr10 [r] 00000000 00000000 020090 h newdt20 [r] 00000000 00000000 newdt10 [r] 00000000 00000000 0200a0 h intpnd20 [r] 00000000 00000000 intpnd10 [r] 00000000 00000000 0200b0 h msgval20 [r] 00000000 00000000 msgval10 [r] 00000000 00000000 0200b4 h to 0200fc h ? system reserved 020100 h ctrlr1 [r, r/w] 00000000 00000001 statr1 [r, r/w] 00000000 00000000 can 1 (mb91v280 only) 020104 h errcnt1 [r] 00000000 00000000 btr1 [r, r/w] 00100011 00000001 020108 h intr1 [r] 00000000 00000000 testr1 [r, r/w] 00000000 00000000 02010c h brper1 [r, r/w] 00000000 00000000 ? 020110 h if1creq1 [r, r/w] 00000000 00000001 if1cmsk1 [r, r/w] 00000000 00000000 020114 h if1msk21 [r, r/w] 11111111 11111111 if1msk11 [r, r/w] 11111111 11111111 020118 h if1arb21 [r/w] 00000000 00000000 if1arb11 [r/w] 00000000 00000000 02011c h if1mctr1 [r, r/w] 00000000 00000000 ? 020120 h if1dta11 [r/w] xxxxxxxx xxxxxxxx if1dta21 [r/w] xxxxxxxx xxxxxxxx 020124 h if1dtb11 [r/w] xxxxxxxx xxxxxxxx if1dtb21 [r/w] xxxxxxxx xxxxxxxx 020130 h to 02013c h system reserved (if1 data mirror, little endian byte ordering) 020140 h if2creq1 [r, r/w] 00000000 00000001 if2cmsk1 [r, r/w] 00000000 00000000 020144 h if2msk21 [r, r/w] 11111111 11111111 if2msk11 [r, r/w] 11111111 11111111 020148 h if2arb21 [r/w] 00000000 00000000 if2arb11 [r/w] 00000000 00000000
mb91270 series 44 (continued) address register block + 0 + 1 + 2 + 3 02014c h if2mctr1 [r, r/w] 00000000 00000000 ? can 1 (mb91v280 only) 020150 h if2dta11 [r/w] xxxxxxxx xxxxxxxx if2dta21 [r/w] xxxxxxxx xxxxxxxx 020154 h if2dtb11 [r/w] xxxxxxxx xxxxxxxx if2dtb21 [r/w] xxxxxxxx xxxxxxxx 020160 h to 02017c h system reserved (if2 data mirror, little endian byte ordering) 020180 h treqr21 [r] 00000000 00000000 treqr11 [r] 00000000 00000000 020190 h newdt21 [r] 00000000 00000000 newdt11 [r] 00000000 00000000 0201a0 h intpnd21 [r] 00000000 00000000 intpnd11 [r] 00000000 00000000 0201b0 h msgval21 [r] 00000000 00000000 msgval11 [r] 00000000 00000000 020200 h ctrlr2 [r, r/w] 00000000 00000001 statr2 [r, r/w] 00000000 00000000 can 2 (mb91v280 only) 020204 h errcnt2 [r] 00000000 00000000 btr2 [r, r/w] 00100011 00000001 020208 h intr2 [r] 00000000 00000000 testr2 [r, r/w] 00000000 00000000 02020c h brper2 [r, r/w] 00000000 00000000 ? 020210 h if1creq2 [r, r/w] 00000000 00000001 if1cmsk2 [r, r/w] 00000000 00000000 020214 h if1msk22 [r, r/w] 11111111 11111111 if1msk12 [r, r/w] 11111111 11111111 020218 h if1arb22 [r/w] 00000000 00000000 if1arb12 [r/w] 00000000 00000000 02021c h if1mctr2 [r, r/w] 00000000 00000000 ? 020220 h if1dta12 [r/w] xxxxxxxx xxxxxxxx if1dta22 [r/w] xxxxxxxx xxxxxxxx 020224 h if1dtb12 [r/w] xxxxxxxx xxxxxxxx if1dtb22 [r/w] xxxxxxxx xxxxxxxx 020230 h to 02023c h system reserved (if1 data mirror, little endian byte ordering) 020240 h if2creq2 [r, r/w] 00000000 00000001 if2cmsk2 [r, r/w] 00000000 00000000
mb91270 series 45 (continued) address register block + 0 + 1 + 2 + 3 020244 h if2msk22 [r, r/w] 11111111 11111111 if2msk12 [r, r/w] 11111111 11111111 can 2 (mb91v280 only) 020248 h if2arb22 [r/w] 00000000 00000000 if2arb12 [r/w] 00000000 00000000 02024c h if2mctr2 [r, r/w] 00000000 00000000 ? 020250 h if2dta12 [r/w] xxxxxxxx xxxxxxxx if2dta22 [r/w] xxxxxxxx xxxxxxxx 020254 h if2dtb12 [r/w] xxxxxxxx xxxxxxxx if2dtb22 [r/w] xxxxxxxx xxxxxxxx 020260 h to 02027c h system reserved (if2 data mirror, little endian byte ordering) 020280 h treqr22 [r] 00000000 00000000 treqr12 [r] 00000000 00000000 020290 h newdt22 [r] 00000000 00000000 newdt12 [r] 00000000 00000000 0202a0 h intpnd22 [r] 00000000 00000000 intpnd12 [r] 00000000 00000000 0202b0 h msgval22 [r] 00000000 00000000 msgval12 [r] 00000000 00000000 034000 h to 03fffc h ? f-bus ram (mb91v280) 03a000 h to 03fffc h ? f-bus ram (mb91f273 (s) / mb91f278 (s) ) 080000 h to 0ffffc h ? flash memory (mb91f273 (s) / mb91f278 (s) )
mb91270 series 46 interrupt vector (continued) interrupt source interrupt number interrupt level interrupt vector dma decimal hexa- decimal register address offset tbr default address rn stop reset 0 00 ?? 3fc h 000ffffc h ?? mode vector 1 01 ?? 3f8 h 000ffff8 h ?? system reserved 2 02 ?? 3f4 h 000ffff4 h ?? system reserved 3 03 ?? 3f0 h 000ffff0 h ?? system reserved 4 04 ?? 3ec h 000fffec h ?? system reserved 5 05 ?? 3e8 h 000fffe8 h ?? system reserved 6 06 ?? 3e4 h 000fffe4 h ?? coprocessor absent trap 7 07 ?? 3e0 h 000fffe0 h ?? coprocessor error trap 8 08 ?? 3dc h 000fffdc h ?? inte instruction 9 09 ?? 3d8 h 000fffd8 h ?? system reserved 10 0a ?? 3d4 h 00fffd4c h ?? system reserved 11 0b ?? 3d0 h 000fffd0 h ?? step trace trap 12 0c ?? 3cc h 000fffcc h ?? nmi request (tool) 13 0d ?? 3c8 h 000fffc8 h ?? undefined instruction exception 14 0e ?? 3c4 h 000fffc4 h ?? nmi request 15 0f 15 (f h ) fixed ? 3c0 h 000fffc0 h ?? external interrupt 0 16 10 icr00 0x440 3bc h 000fffbc h 6 ? external interrupt 1 17 11 icr01 0x441 3b8 h 000fffb8 h 7 ? external interrupt 2 18 12 icr02 0x442 3b4 h 000fffb4 h ?? external interrupt 3 19 13 icr03 0x443 3b0 h 000fffb0 h ?? external interrupt 4 20 14 icr04 0x444 3ac h 000fffac h ?? external interrupt 5 21 15 icr05 0x445 3a8 h 000fffa8 h ?? external interrupt 6 22 16 icr06 0x446 3a4 h 000fffa4 h ?? external interrupt 7 23 17 icr07 0x447 3a0 h 000fffa0 h ?? reload timer 0 24 18 icr08 0x448 39c h 000fff9c h 8 ? reload timer 1 25 19 icr09 0x449 398 h 000fff98 h 9 ? reload timer 2 26 1a icr10 0x44a 394 h 000fff94 h 10 ? lin-uart 0 reception 27 1b icr11 0x44b 390 h 000fff90 h 0stop lin-uart 0 transmission 28 1c icr12 0x44c 38c h 000fff8c h 3 ? lin-uart 1 reception 29 1d icr13 0x44d 388 h 000fff88 h 1stop lin-uart 1 transmission 30 1e icr14 0x44e 384 h 000fff84 h 4 ?
mb91270 series 47 (continued) interrupt source interrupt number interrupt level interrupt vector dma decimal hexa- decimal register address offset tbr default address rn stop lin-uart 2 reception 31 1f icr15 0x44f 380 h 000fff80 h 2stop lin-uart 2 transmission 32 20 icr16 0x450 37c h 000fff7c h 5 ? can 0 33 21 icr17 0x451 378 h 000fff78 h ?? can 1/icu 6/7* 34 22 icr18 0x452 374 h 000fff74 h ?? can 2* 35 23 icr19 0x453 370 h 000fff70 h ?? lin-uart 3/5 reception 36 24 icr20 0x454 36c h 000fff6c h ?? lin-uart 3/5 transmission 37 25 icr21 0x455 368 h 000fff68 h ?? lin-uart 4/6 reception 38 26 icr22 0x456 364 h 000fff64 h ?? lin-uart 4/6 transmission 39 27 icr23 0x457 360 h 000fff60 h ?? i 2 c 0 40 28 icr24 0x458 35c h 000fff5c h ?? i 2 c 1/udc 2 41 29 icr25 0x459 358 h 000fff58 h ?? i 2 c 2 42 2a icr26 0x45a 354 h 000fff54 h ?? a/d converter 43 2b icr27 0x45b 350 h 000fff50 h 14 ? rtc 44 2c icr28 0x45c 34c h 000fff4c h ?? udc 1 45 2d icr29 0x45d 348 h 000fff48 h ?? main oscillation stabilization wait timer 46 2e icr30 0x45e 344 h 000fff44 h ?? tbt overflow 47 2f icr31 0x45f 340 h 000fff40 h ?? ppg 0/1/4/5 48 30 icr32 0x460 33c h 000fff3c h ?? ppg 2/3/6/7 49 31 icr33 0x461 338 h 000fff38 h ?? ppg 8/9/c/d 50 32 icr34 0x462 334 h 000fff34 h ?? ppg a/b/e/f 51 33 icr35 0x463 330 h 000fff30 h ?? frt 0/1 52 34 icr36 0x464 32c h 000fff2c h ?? frt 2/3 53 35 icr37 0x465 328 h 000fff28 h ?? icu 0/1/2/3 54 36 icr38 0x466 324 h 000fff24 h ?? icu 4/5 55 37 icr39 0x467 320 h 000fff20 h ?? ocu 0/1/2/3 udc 3 56 38 icr40 0x468 31c h 000fff1c h ?? ocu 4/5/6/7 57 39 icr41 0x469 318 h 000fff18 h ?? udc 0 58 3a icr42 0x46a 314 h 000fff14 h ?? external interrupt 8/9/10/11 59 3b icr43 0x46b 310 h 000fff10 h ?? external interrupt 12 to 39* 60 3c icr44 0x46c 30c h 000fff0c h ?? rom correction interrupt 61 3d icr45 0x46d 308 h 000fff08 h ?? dma 62 3e icr46 0x46e 304 h 000fff04 h ?? delay interrupt 63 3f icr47 0x46f 300 h 000fff00 h ??
mb91270 series 48 (continued) * : can1, can2, and external interrupts 16 to 39 are only available on the mb91v280. interrupt source interrupt number interrupt level interrupt vector dma decimal hexa- decimal register address offset tbr default address rn stop system reserved (realos) 64 40 ?? 2fc h 000ffefc h ?? system reserved (realos) 65 41 ?? 2f8 h 000ffef8 h ?? system reserved 66 42 ?? 2f4 h 000ffef4 h ?? system reserved 67 43 ?? 2f0 h 000ffef0 h ?? system reserved 68 44 ?? 2ec h 000ffeec h ?? system reserved 69 45 ?? 2e8 h 000ffee8 h ?? system reserved 70 46 ?? 2e4 h 000ffee4 h ?? system reserved 71 47 ?? 2e0 h 000ffee0 h ?? system reserved 72 48 ?? 2dc h 000ffedc h ?? system reserved 73 49 ?? 2d8 h 000ffed8 h ?? system reserved 74 4a ?? 2d4 h 000ffed4 h ?? system reserved 75 4b ?? 2d0 h 000ffed0 h ?? system reserved 76 4c ?? 2cc h 000ffecc h ?? system reserved 77 4d ?? 2c8 h 000ffec8 h ?? system reserved 78 4e ?? 2c4 h 000ffec4 h ?? system reserved 79 4f ?? 2c0 h 000ffec0 h ?? used by int instruction 80 to 255 50 to ff ?? 2bc h to 000 h 000ffebc h to 000ffc00 h ??
mb91270 series 49 pin states in ea ch cpu state ? pin states in single-chip mode (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst p00 int8 sin5 p00 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 p01 int9 sot5 p01 p02 int10 sck5 p02 p03 int11 sin6 p03 p04 int12 sot6 p04 p05 int13 sck6 p05 p06 int14 p06 p07 int15 p07 p10 tin1 p10 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p11 tot1 p11 p12 sin3 int11r p12 *1 p13 sot3 p13 p14 sck3 p14 p15 sin4 p15 p16 sot4 p16 p17 sck4 p17 p20 ppg9 p20 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p21 ppgb p21 p22 ppgd p22 p23 ppgf p23 p24 in0 p24 p25 in1 p25 p26 in2 p26 p27 in3 p27
mb91270 series 50 (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0hiz = 1 init rst p30 in4 p30 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p31 in5 p31 p32 rx2 int10r p32 *1 p33 tx2 p33 p34 out4 p34 p35 out5 p35 p36 out6 p36 p37 out7 p37 p40 ? p40 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p41 ? p41 p42 in6 int9r p42 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 p43 in7 p43 p44 sda0 frck0 p44 p45 scl0 frck1 ain2 p45 p46 sda1 bin2 p46 p47 scl1 zin2 p47 p50 an8 sin2 p50 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p51 an9 sot2 p51 p52 an10 sck2 p52 p53 an11 bin1 p53 p54 an12 ain1 p54
mb91270 series 51 (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst p55 an13 zin1 p55 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p56 an14 dao0 p56 p57 an15 dao1 p57 p60 an0 ppg0 p60 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p61 an1 ppg2 p61 p62 an2 ppg4 p62 p63 an3 ppg6 p63 p64 an4 ppg8 p64 p65 an5 ppga p65 p66 an6 ppgc p66 p67 an7 ppge p67 p70 an16 int0 p70 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 p71 an17 int1 p71 p72 an18 int2 p72 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p73 an19 int3 p73 p74 an20 int4 p74 p75 an21 int5 p75 p76 an22 int6 sda2 p76 p77 an23 int7 scl2 p77
mb91270 series 52 (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst p80 tin0 adtg int12r p80 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 p81 tot0 ckot int13r p81 p82 sin0 tin2 int14r p82 p83 sot0 tot2 p83 p84 sck0 int15r p84 *1 p85 sin1 p85 p86 sot1 p86 p87 sck1 p87 p90 ppg1 p90 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect p91 ppg3 ain3 p91 p92 ppg5 bin3 p92 p93 ppg7 zin3 p93 p94 out0 ain0 p94 p95 out1 bin0 p95 p96 out2 zin0 p96 p97 out3 p97 pa0 rx0 int8r pa0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 pa1 tx0 pa1 pb0 int8-2 sin5-2 pb0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *2
mb91270 series 53 (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst pb1 int9-2 sot5-2 pb1 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *2 pb2 int10-2 sck5-2 pb2 pb3 int11-2 sin6-2 pb3 pb4 int12-2 sot6-2 pb4 pb5 int13-2 sck6-2 pb5 pc0 out4-2 int0r pc0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 pc1 out5-2 int1r pc1 pc2 sin3-2 int2r pc2 pc3 sot3-2 int3r pc3 pc4 sck3-2 int4r pc4 pc5 sin4-2 int5r pc5 pc6 sot4-2 int6r pc6 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect pc7 sck4-2 int7r pc7
mb91270 series 54 (continued) port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst pd0 ppg9-2 int16 pd0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 pd1 ppgb-2 int17 pd1 pd2 ppgd-2 int18 pd2 pd3 ppgf-2 int19 pd3 pd4 in0-2 int20 pd4 pd5 in1-2 int21 pd5 pd6 in2-2 int22 pd6 pd7 in3-2 int23 pd7 pe0 int24 pe0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect pe1 int25 pe1 pe2 int26 pe2 pe3 int27 pe3 pe4 int28 pe4 pe5 int29 pe5 pe6 int30 pe6 pe7 int31 pe7 pf0 int32 pf0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect pf1 int33 pf1 pf2 int34 pf2 pf3 int35 pf3 pf4 int36 pf4 pf5 int37 pf5 pf6 int38 pf6 pf7 int39 pf7
mb91270 series 55 (continued) *1 : pins become inputs and can be used to wakeup from stop mode when the corresponding external interrupt is enabled in enir and the pin is selected as an external interrupt input pin in eissr. *2 : pins will be available to input and can be used to restore from the stop mode when the corres ponding external interrupt is enabled in enir and the pin is selected as an external interrupt input pin in epfr. input enabled : this indicates that the input function is available in this state. input disconnect : disconnects the external input at the input gate immediately adjacent to the pin . an "l" level is passed to internal circuits. output hi-z : turns the pin to high-impedance by preventing the pin drive transistor from driving. output maintained : indicates that pins maintain the output level they had prior to changing to this mode. in other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. maintain previous state : indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate. port name specified function name at initialization sleep sub sleep in stop mode in rtc mode remarks function name internal rom mode vector (md2-0 = 000) hiz = 0 hiz = 1 init rst pg0 an24 pg0 output hi-z input enabled output hi-z input enabled maintain previous state maintain previous state output hi-z input disconnect *1 pg1 an25 pg1 pg2 an26 pg2 pg3 an27 pg3 pg4 an28 pg4 pg5 an29 pg5 pg6 an30 pg6 pg7 an31 pg7
mb91270 series 56 pin states in external bus mode the external bus interface pins will be in an output mode wh ile the device is in the se ttings initialization (init) state. the pins is in the hi-z state while the init pin is at the ?l? level. the va lue listed in the table is output when the init pin goes to the ?h? level. the external bus interface output functions for ports 2, 3, 9, e, and f can be disabled by setting epfr. the symbols in the table indicate : b : external bus interface function mode (epfr = 0) p : general-purpose port or peripheral function mode (epfr = 1) (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p00 ad00 int8 sin5 ad00 output hi-z input enabled output hi-z input enabled address output (mpx) output hi-z input enabled (data) output hi-z input discon- nect *1 p01 ad01 int9 sot5 ad01 p02 ad02 int10 sck5 ad02 p03 ad03 int11 sin6 ad03 p04 ad04 int12 sot6 ad04 p05 ad05 int13 sck6 ad05 p06 ad06 int14 ad06 p07 ad07 int15 ad07
mb91270 series 57 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p10 ad08 tin1 ad08 output hi-z input enabled output hi-z input enabled address output (mpx) output hi-z input enabled (data) output hi-z input disconnect p11 ad09 tot1 ad09 p12 ad10 sin3 int11r ad10 *1 p13 ad11 sot3 ad11 p14 ad12 sck3 ad12 p15 ad13 sin4 ad13 p16 ad14 sot4 ad14 output hi-z input enabled output hi-z input enabled address output (mpx) output hi-z input enabled (data) output hi-z input disconnect p17 ad15 sck4 ad15 p20 a16 ppg9 a16 output 0xff output hi-z input enabled b : address output p : maintain previous state output hi-z input disconnect *2 p21 a17 ppgb a17 p22 a18 ppgd a18 p23 a19 ppgf a19 p24 a20 in0 a20 p25 a21 in1 a21 p26 a22 in2 a22 p27 a23 in3 a23
mb91270 series 58 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p30 as in4 as ?h? level output output hi-z input enabled b : ?h? level output p : maintain previous state output hi-z input disconnect *2 p31 rd in5 rd p32 wr0 rx2 int10r wr0 *1 *2 p33 wr1 tx2 wr1 *2 p34 out4 p34 output hi-z input enabled maintain previous state p35 out5 p35 p36 rdy out6 rdy b : output hi-z p : maintain previous state p37 sysclk out7 p37 clock output b : clock output p : maintain previous state b : ?h? level output p : maintain previous state *2 p40 ? p40 same as single-chip mode p41 ? p41 p42 in6 int9r p42 p43 in7 p43 p44 sda0 frck0 p44
mb91270 series 59 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p45 scl0 ain2 frck1 p45 same as single-chip mode p46 sda1 bin2 p46 p47 scl1 zin2 p47 p50 an8 sin2 p50 same as single-chip mode p51 an9 sot2 p51 p52 an10 sck2 p52 p53 an11 bin1 p53 p54 an12 ain1 p54 p55 an13 zin1 p55 p56 an14 dao0 p56 p57 an15 dao1 p57 p60 an0 ppg0 p60 same as single-chip mode p61 an1 ppg2 p61 p62 an2 ppg4 p62 p63 an3 ppg6 p63 p64 an4 ppg8 p64 p65 an5 ppga p65 p66 an6 ppgc p66 p67 an7 ppge p67
mb91270 series 60 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p70 an16 int0 p70 same as single-chip mode p71 an17 int1 p71 p72 an18 int2 p72 p73 an19 int3 p73 p74 an20 int4 p74 p75 an21 int5 p75 p76 an22 int6 sda2 p76 p77 an23 int7 scl2 p77 p80 tin0 adtg int12r p80 same as single-chip mode p81 tot0 ckot int13r p81 p82 sin0 tin2 int14r p82 p83 sot0 tot2 p83 p84 sck0 int15r p84 p85 sin1 p85 p86 sot1 p86 p87 sck1 p87
mb91270 series 61 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) p90 cs0 ppg1 cs0 ?h? level output output hi-z input enabled b : ?h? level output p : maintain previous state output hi-z input disconnect *2 p91 cs1 ppg3 ain3 cs1 p92 cs2 ppg5 bin3 cs2 p93 cs3 ppg7 zin3 cs3 p94 out0 ain0 p94 same as single-chip mode p95 out1 bin0 p95 p96 out2 zin0 p96 p97 out3 p97 pa0 rx0 int8r pa0 same as single-chip mode pa1 tx0 pa1 pb0 int8-2 sin5-2 pb0 same as single-chip mode pb1 int9-2 sot5-2 pb1 pb2 int10-2 sck5-2 pb2 pb3 int11-2 sin6-2 pb3 pb4 int12-2 sot6-2 pb4 pb5 int13-2 sck6-2 pb5
mb91270 series 62 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) pc0 out4-2 int0r pc0 same as single-chip mode pc1 out5-2 int1r pc1 pc2 sin3-2 int2r pc2 pc3 sot3-2 int3r pc3 pc4 sck3-2 int4r pc4 pc5 sin4-2 int5r pc5 pc6 sot4-2 int6r pc6 pc7 sck4-2 int7r pc7 pd0 ppg9-2 int16 pd0 same as single-chip mode pd1 ppgb-2 int17 pd1 pd2 ppgd-2 int18 pd2 pd3 ppgf-2 int19 pd3 pd4 in0-2 int20 pd4 pd5 in1-2 int21 pd5 same as single-chip mode pd6 in2-2 int22 pd6 pd7 in3-2 int23 pd7
mb91270 series 63 (continued) port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) pe0 a00 int24 a00 ?h? level output output hi-z input enabled b : address output p : maintain previous state output hi-z input disconnect *1 *2 pe1 a01 int25 a01 pe2 a02 int26 a02 pe3 a03 int27 a03 pe4 a04 int28 a04 pe5 a05 int29 a05 pe6 a06 int30 a06 pe7 a07 int31 a07 pf0 a08 int32 a08 ?h? level output output hi-z input enabled b : address output p : maintain previous state output hi-z input disconnect *1 *2 pf1 a09 int33 a09 pf2 a10 int34 a10 pf3 a11 int35 a11 pf4 a12 int36 a12 pf5 a13 int37 a13 pf6 a14 int38 a14 pf7 a15 int39 a15 pg0 an24 pg0 same as single-chip mode pg1 an25 pg1 pg2 an26 pg2 pg3 an27 pg3
mb91270 series 64 (continued) *1 : pins become inputs and can be used to wakeup fr om stop mode when the corresponding external interrupt is enabled in enir and the pin is selected as an external interrupt input pin in eissr. *2 : outputs go to hi-z at power on or while the init pin is at the ?l? level starti ng from the fa lling edge on the init pin. input enabled : this indicates that the i nput function is available in this state. input disconnect : disconnects the external input at the input gate immediately adjacent to the pin . an "l" level is passed to internal circuits. output hi-z : turns the pin to high-impedance by preventing the pin drive transistor from driving. output maintained : indicates that pins maintain the output level they had prior to changing to this mode. in other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. maintain previous state : indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate. port name specified function name at a initial/reset sleep sub sleep in stop mode in rtc mode remarks function name initial value hiz = 0 hiz = 1 external rom mode vector (md2-0 = 001) internal rom mode vector (md2-0 = 000) pg4 an28 pg4 same as single-chip mode pg5 an29 pg5 pg6 an30 pg6 pg7 an31 pg7
mb91270 series 65 electrical characteristics 1. absolute maximum ratings *1 : ensure that av cc does not exceed v cc when the power is turned on. *2 : the maximum output current specifies the peak current for an individual pin. *3 : the average output current specifies the average current that flows through an individual pin over a period of 100 ms. the average value is the operating current operation ratio. *4 : the total average output current specifies the average current that flows through all of the pins over a period of 100 ms. the average value is the operating current operation ratio. *5 : the +b input rating specifies the current for an individual pin. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v av cc = v cc * 1 avrh v ss ? 0.3 v ss + 6.0 v av cc avrh input voltage v i v ss ? 0.3 v cc + 0.3 v output voltage v o v ss ? 0.3 v cc + 0.3 v ?l? level maximum output current* 2 i ol1 ? 15 ma ?l? level average output current* 3 i olav1 ? 4ma ?l? level total maximum output current i ol1 ? 120 ma ?l? level total average output current* 4 i olav1 ? 50 ma ?h? level maximum output current* 2 i oh1 ? ? 15 ma ?h? level average output current* 3 i ohav1 ? ? 4ma ?h? level total maximum output current i oh1 ? ? 120 ma ?h? level total average output current* 4 i ohav1 ? ? 50 ma power consumption p d ? 500 mw operating temperature t a ? 40 + 105 c single-chip mode ? 40 + 85 c external bus mode storage temperature tstg ? 55 + 150 c + b input rating (maximum clamp current) i ihh ? 2ma*5 [pins applicable] p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0, pa1, pb0 to pb5, pc0 to pc 7, pd0 to pd7, pe0 to pe7, pf0 to pf7, pg0 to pg7 (+b input to p56 and p57 not allowed on the mb91v280.)
mb91270 series 66 [ for +b input (12v to 16v) ] sample recommended circuits: 1. do not connect the +b potential directly to a microcontroller pin. 2. always place a current-limiting resistor between the +b signal and microcontroller pins. i ihh = 2ma per pin (max) [during normal operation and during transients such as when turning the power on or off] 3. although the internal protection diode in the microcon troller causes the potential between the +b input-limit- ing resistor and microcontroller pin to be equal to the v cc + on voltage of the protection diode, do not use a circuit structure that obstructs this operation or that causes this potential to be exceeded. i ihh protection diode current-limiting resistor + b input (0 v to 16 v)
mb91270 series 67 2. recommended operating conditions (v ss = av ss = 0.0 v) * : refer to the following figure for connection of smoothing capacitor cs. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc av cc 4.5 5.5 v normal operation v cc av cc 3.5 5.5 v excluding a/d converter operation v cc 3.0 5.5 v maintain ram data during stop mode smoothing capacitor* c s 1 ( 50 % tolerance) f use a ceramic capacitor or a capacitor of similar frequency characteristics. on the vcc pin, use a bypass capacitor with a larger capacity than that of cs. operating temperature t a ? 40 + 105 c single-chip mode ? 40 + 85 c external bus mode c s c v ss av ss ? c pin connection diagram
mb91270 series 68 3. dc characteristics (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) (continued) parameter sym- bol pin name condi- tions value unit remarks min typ max ?h? level input voltage v ihs ?? 0.8 v cc ? v cc + 0.3 v cmos automotive input v ihc ?? 0.7 v cc ? v cc + 0.3 v cmos schmitt input v iht ?? 2.1 ? v cc + 0.3 v ttl input* 1 v ihm md0 md1 md2 ? v cc ? 0.3 ? v cc + 0.3 v v ihi init ? 0.8 v cc ? v cc + 0.3 v ?l? level input voltage v ils ?? v ss ? 0.3 ? 0.5 v cc v cmos automotive input v ilc ?? v ss ? 0.3 ? 0.3 v cc v cmos schmitt input v ilt ?? v ss ? 0.3 ? 0.8 v ttl input* 1 v ilm md0 md1 md2 ? v ss ? 0.3 ? v ss + 0.3 v v ili init ? v ss ? 0.3 ? 0.2 v cc v power supply current i cc v cc *2 ? 100 120 ma normal operation* 11 *3 ? 70 90 ma normal operation* 11 i ccs v cc *4 ? 40 55 ma sleep operation* 11 *5 ? 20 30 ma sleep operation* 11 i ccl v cc *6 ? 400 700 a sub operation i ccsl v cc *7 ? 300 600 a sub-sleep operation i ccr32 v cc *8 ? 200 300 a 32 khz clock operation * 12 i ccr4 v cc *9 ? 700 1000 a 4 mhz clock operation* 12 i cch v cc *10 ? 20 100 astop input leak current i il ?? ? 5 ? 5 a all input pins input ca- pacitance c in ?? ? 515pf pull-up resistor r up ?? 25 50 100 k ? selectable except for p44 to p47, p56, p57, p76, and p77 pull-down resistor r down ?? 25 50 100 k ? selectable except for p44 to p47, p56, p57, p76, and p77
mb91270 series 69 (continued) *1 : in external bus mode, only p00 to p07, p10 to p17, and p36 can be selected. *2 : clkb = 32 mhz, clkp = 32 mhz, clkt = 16 mhz, canclk = 16 mhz *3 : clkb = 32 mhz, clkp = 8 mhz, clkt = 4 mhz, canclk = 8 mhz *4 : cpu halted for case *2. *5 : cpu halted for case *3. *6 : clkb = clkp = clkt = canclk = 32 khz, t a = + 25 c *7 : cpu halted for case *6 *8 : cpu and peripheral circuits halted, main oscillation halted, 32 khz clock operation, t a = + 25 c *9 : cpu and peripheral circuits halted, sub- oscillation halted, 4 mh z clock operation, t a = + 25 c *10 : cpu and peripheral circuits halt ed, all oscillation circuits halted, t a = + 25 c *11 : the current consumptio n values for normal operation mode an d sleep mode assume that the peripheral circuits are operating at maximum capacity. *12 : the current consumption value for clock mode operation does not include the consumption of the external oscillator. parameter symbol pin name conditions value unit remarks min typ max ?h? level output voltage v oh ? i oh = ? 4 ma v cc ? 0.5 ?? v other than p44 to p47, p76 and p77 v ohi p44 to p47 p76, p77 i oh = ? 3 ma v cc ? 0.5 ?? v pins also used for i 2 c ?l? level output voltage v ol ? i ol = 4 ma ?? 0.4 v other than p44 to p47, p76 and p77 v oli p44 to p47 p76, p77 i ol = 3 ma ?? 0.4 v pins also used for i 2 c
mb91270 series 70 4. flash memory program and erase characteristics * : calculated value based on technology reliability test data. (value calculated using the arrhenius equation for the burn-in test results with an average temperature of + 85 c.) parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 15 s excludes time for internal write prior to erase. chip erase time t a = + 25 c v cc = 5.0 v ? 14 ? s excludes time for internal write prior to erase. half-word write time t a = + 25 c v cc = 5.0 v ? 16 3600 s excludes system-level overhead time. chip write time t a = + 25 c v cc = 5.0 v ? 2.1 ? s excludes system-level overhead time. erase/write cycle ? 10000 ?? cycle data retention time average t a = + 85 c 20* ?? year
mb91270 series 71 5. ac characteristics (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) parameter sym- bol pin name conditions value unit remarks min typ max source oscillation clock frequency f c x0, x1 ? ? 412mhz f ca x0a, x1a ? 32.768 100 khz source oscillation clock cycle time t cyl x0, x1 83.3 250 ? ns t cyll x0a, x1a 10 30.5 ? s input clock pulse width p wh p wl x0 30 ?? ns use a duty ratio in the range 40 % to 60 % . input clock rise time and fall time tcr, tcf x0 ?? 5ns when external clock is used internal operation clock frequency f cp ??? 32 mhz when main clock, pll clock are used. internal operation clock cycle time t cp ? 31.25 ?? ns when main clock, pll clock are used. tcr 0.2 v cc 0.8 v cc p wl tcf x0 p wh t cyl x0, x1 clock timing
mb91270 series 72 ? operation assurance range relation between internal operation clock frequency and power supply voltage relation between oscillation clock fr equency and internal operation clock sample oscillation circuit internal operation clock frequency main clock pll clock pll multi- plication rate = 2 pll multi- plication rate = 3 pll multi- plication rate = 4 pll multi- plication rate = 6 pll multi- plication rate = 8 oscillation clock frequency 4 mhz 2 mhz 8 mhz 12 mhz 16 mhz 24 mhz 32 mhz 8 mhz 4 mhz 16 mhz 24 mhz 32 mhz ?? 12 mhz 6 mhz 24 mhz ???? 5.5 4.5 3 .5 2 83 2 note : use a pll operation st abilization wait time of 500 s or more. internal operation clock frequency f cp (mhz) power supply voltage v cc (v) pll operation guarantee range recommended operation range (a/d converter accuracy guarantee range) operation assurance range c2 c1 r x0 x1
mb91270 series 73 the ac standards assume the following measurement reference voltages. input signal waveform output signal waveform hysteresis input pin output pin hysteresis input pin (automotive) ? ttl input pin ? 0.3 v cc 0.7 v cc 0.4 v 4.6 v 0.5 v cc 0.8 v cc 0.8 v 2.1 v
mb91270 series 74 ? reset input (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) the following reset input standard should be satisfied as ram data protection standard. * : t cp : period of the internal base clock. to protect ram data, input init of 256 t cp or more before voltage drop at v cc = 3.5 v or less. parameter symbol pin name conditions value unit remarks min max init input time t intl init ? 10 ? s 300 ? sat stop 8 ? ms at power-on v cc (v) voltage drop time extarnal reset input standard (init ) min max min max at drop of 4.0 3.5 v 256 t cp * ? 300 s ? init 0.2 v cc 0.2 v cc t intl init v cc 4 v 3 .5 v 3 .5 v 256 t cp 300 s or more
mb91270 series 75 ? uart timing (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) note : these are ac characteristics in the clock synchronous mode. c l is the load capacitance connected to the pin for testing. parameter sym- bol pin name conditions value unit remarks min max serial clock cycle time t scyc sckx ? 8 t cp ? ns internal shift clock mode output pin capacitance is c l = 80 pf + 1 ttl sck sot delay time t slov sckx sotx ? 80 + 80 ns valid sin sck t ivsh sckx sinx 100 ? ns sck valid sin hold time t shix 60 ? ns serial clock ?h? pulse width t shsl sckx ? 4 t cp ? ns external shift clock mode output pin capacitance is c l = 80 pf + 1 ttl serial clock ?l? pulse width t slsh 4 t cp ? ns sck sot delay time t slov sckx sotx ? 150 ns valid sin sck t ivsh sckx sinx 60 ? ns sck valid sin hold time t shix 60 ? ns
mb91270 series 76 2.4 v 2.4 v 0.8 v 0.8 v sinx sotx sckx t scyc t slov t shix t ivsh 0.8 v cc 0.5 v cc 0.8 v cc 0.5 v cc 0.8 v 2.4 v 0.6 v cc 0.6 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.5 v cc 0.8 v cc 0.5 v cc 0.8 v sinx sotx sckx t slsh t slov t shix t ivsh t shsl ? internal shift clock mode ? external shift clock mode
mb91270 series 77 ? timer input timing (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tinx inx ? 4 t cp ? ns ? 0. 8 v cc 0. 8 v cc 0.5 v cc 0.5 v cc tinx inx t tiwl t tiwh
mb91270 series 78 6. electrical characteristics for the a/d converter ? electrical characteristics (t a : recommended operating conditions, v cc = 5.0 v 10 % , v ss = a v ss = 0.0 v) *1 : for f cp = 32 mhz, t smp = (rext + rin) cin 7 = st clkp period = 2 ch 31.25 ns = 1.375 s *2 : for f cp = 32 mhz, t cmp = ckin 11 = ct clkp period 11 = 4 h 31.25 ns 11 = 1.375 s *3 : for f cp = 32 mhz, this is equivalent to the conversion time per channel when t smp and t cmp are selected. *4 : specifies the power supply current when the a/d converter is not operating and the cpu is in stop mode (vcc = avcc = avrh = 5.0 v) notes : ? the error becomes proportionately larger as the avrh voltages go lower. ? use the device with external circuits of the following output impedance r s for analog inputs : external circuit output impedance r s = 5 k ? (max) ? if the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. ? if inserting a capacitor between the external circuit and an input pin to prevent direct current flow, select a capacitance several thousand times larger than c sh to minimize the capacitive voltage divider effect due to the c sh sampling capacito r in the chip. parameter sym- bol pin name value unit remarks min typ max resolution ?? ?? 10 bit total error ?? ?? 3.0 lsb nonlinear error ?? ?? 2.5 lsb differential linear error ?? ?? 1.9 lsb zero transition voltage v ot an0 to an23 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 1 lsb = (avrh ? av ss ) / 1024 full-scale transition voltage v fst an0 to an23 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb v sampling time t smp ? 1.375 ?? s*1 compare time t cmp ? 1.375 ?? s*2 a/d conversion time t cnv ? 2.750 ?? s*3 analog port input current i ain an0 to an23 ?? 10 av avss v ain v avcc analog input voltage v ain an0 to an23 0 ? avrh v reference voltage avrh avrh 4.0 ? av cc v power supply current i a av cc ? 2.4 4.7 ma i ah ?? 5 a*4 reference voltage supplying current i r avrh ? 600 900 av avrh = 5.0 v i rh ?? 5 a*4 interchannel disparity ? an0 to an31 ?? 4lsb
mb91270 series 79 r s r s h c s h v s ? analog input equivalent circuit microcontroller internal circuit external circuit input pin an0 input pin an7 analog channel selector s/h circuit comparator < recommended parameter values for each component > r s : under 5 k ? r sh = approx. 2.5 k ? c sh = approx. 10 pf note : parameter values for each component are indicative design values.
mb91270 series 80 ? definition of terminology resolution represents the change in analog signal enabled to be detected by the a/d converter. for 10-bit conversion, the analog voltage can be resolved into 2 10 = 1024 increments. total error this error indicates the difference between actual and theoretical values, and is the total value of errors that results from offset error, gain error, nonlinear error, and noise. linearity error represents the difference between the actual conversion characteristic and the line between the zero transition point (?00 0000 0000? ?00 0000 0001?) and full scale transition point (?11 1111 1110? ?11 1111 1111?). differential linear error deviation of input voltage, which is required for changing output code by 1 lsb, from a desired value.
mb91270 series 81 11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 v ot v nt 1 lsb n + v ot v fst v (n + 1)t ? conversion characteristics for 10-bit a/d converter digital output analog input linearity error linearity error = v nt ? (1 lsb n + v ot ) 1 lsb [lsb] differential linear error = v ( n + 1 ) t ? v nt 1 lsb ? 1 1 lsb = v fst ? v ot 1022 v ot = av ss + 0.5 lsb [v] ( theoretical value ) v fst = avrh ? 1.5 lsb [v] ( theoretical value ) [lsb] v fst = digital output voltage at which transition from (n ? 1) to n occurs.
mb91270 series 82 ordering information part number package remarks mb91v280cr 401-pin ceramic pga (pga-401c-a02) evaluation model mb91f273spmc 100-pin plastic lqfp (fpt-100p-m05) single clock model mb91f273pmc 100-pin plastic lqfp (fpt-100p-m05) dual clock model mb91f278spmc 100-pin plastic lqfp (fpt-100p-m05) single clock model MB91F278PMC 100-pin plastic lqfp (fpt-100p-m05) dual clock model
mb91270 series 83 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 401-pin cer a mic pga le a d pitch 2.54 inter s titi a l pin m a trix 3 7 s e a ling method met a l s e a l 401-pin cer a mic pga (pga-401c-a02) (pga-401c-a02) 4 8 .26 0.55 (1.900 .022) s q index area 1994 fujit s u limited r401002 s c-2-2 2.54 (.100) typ 0.40 0.10 (.016 .004) dia 45.72 (1. 8 00) ref 1.20 0.25 (.047 .010) 5.27 (.207) max 3 .40 0.40 (.1 3 4 .016) 1.00 (.0 3 9) dia typ (4 plc s ) extra index pin 1.02 (.040) c typ (4 plc s ) c dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s .
mb91270 series 84 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.65g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m05) (fpt-100p-m05) c 200 3 fujit s u limited f100007 s -c-4-6 14.000.10(.551.004) s q 16.000.20(.6 3 0.00 8 ) s q 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.1450.055 (.0057.0022) 0.0 8 (.00 3 ) "a" index .059 ?.004 +.00 8 ?0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb91270 series 85 main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results ? ? changed the name of the series as follows: mb91270/280 series mb91270 series ? ? changed the following part numbers: mb91f272/f272s/v280 mb91f273 (s) /f278(s) / mb91v280 2 features ? built-in memory changed the table due to the change of part numbers 3 features ? i/o port changed ? ? max 120 ports? to ? ? max 82 ports? 5 product lineup changed the table of the product lineup due to the change of part numbers. 6 pin assignment changed the pin names 7, 10, 11, 14 pin function changed the pin names 28 memory map changed the memory map due to the change of part numbers 33 i/o map changed the block name for the 00015c h , 000160 h 45 changed the block names for 03a000 h to 03fffc h , 080000 h to 0ffffc h 46 interrupt vector changed the interrupt source instruction break exception system reserved, operand break trap system reserved 55 pin states in each cpu state ? pin states in single-chip mode changed the description in *2 56, 58, 61, 64 pin states in each cpu state ? pin states in external bus mode changed the pin names 82 ordering information changed the table due to the change of part numbers
mb91270 series 86 memo
mb91270 series 87 memo
fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited strategic business development dept.

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